Well formation For CMOS devices integrated circuit structures

Details Well formation For CMOS devices integrated circuit structures Well formation For CMOS devices integrated circuit structures

1998-12-08

2000-11-07

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257371, 257372, H01L 2976

Patent

active

061440760

ABSTRACT:
A multiple well formation is provided in a CMOS region of a semiconductor substrate to provide enhanced latchup protection for one or more CMOS transistors formed in the wells. The structure comprises an N well extending from the substrate surface down into the substrate, a buried P well formed in the substrate beneath the N well, a second P well extending from the substrate surface down into the substrate, and an isolation region formed in the substrate between the N well and the second P well. The buried P well may extend beneath both the N well and the second P well in the substrate. In a preferred embodiment of the invention, the N well and the second P well are each implanted in the substrate at an energy level sufficient to provide a dopant concentration peak in the substrate below the depth of the isolation region to provide punch through protection and to provide a channel stop beneath the isolation region by proving a P-N junction between the N well and P well beneath the isolation region. The dopant concentration level peak of the dopants forming the buried P well in the substrate will be located below the dopant concentration level peak of the N well a minimum distance sufficient to inhibit reduction of the effective depth of the N well, and a maximum distance not exceeding the maximum distance which will still provide enhanced latchup protection to one or more transistors formed in the CMOS region.

REFERENCES:
patent: 5045898 (1991-09-01), Chen et al.
patent: 5304833 (1994-04-01), Shigeki et al.
patent: 5668775 (1997-09-01), Hidaka
patent: 5869879 (1999-02-01), Fulford, Jr. et al.

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