Well-based method for achieving low capacitance diffusion patter

Details Well-based method for achieving low capacitance diffusion patter Well-based method for achieving low capacitance diffusion patter

1997-05-28

1999-11-30

Hoff, Marc S.

Boots, shoes, and leggings

702150, H01L 2100

Patent

active

059930403

ABSTRACT:
An automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate. In one embodiment, the present invention determines the locations of well regions on a semiconductor substrate. The present invention also determines the locations of interconnect lines on the semiconductor substrate. Next, the present invention creates a union of the location of the well regions on the semiconductor substrate and the location of the interconnect lines on the semiconductor substrate. The present invention uses this union to define allowable locations for placement of fill pattern diffusion regions on the semiconductor substrate such that the fill pattern diffusion regions are not disposed under the interconnect lines.

REFERENCES:
patent: 4753901 (1988-06-01), Ellsworth et al.
patent: 5278105 (1994-01-01), Eden et al.

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