Weakly ordered processing systems and methods

Details Weakly ordered processing systems and methods Weakly ordered processing systems and methods

2011-04-05

2011-04-05

Kim, Hong (Department: 2185)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S107000, C710S306000, C710S315000, C711S154000, C711S152000, C711S168000, C712S225000, C712S216000

Reexamination Certificate

active

07921249

ABSTRACT:
The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.

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