Weak bit testing

Details Weak bit testing Weak bit testing

2002-04-10

2003-09-02

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S154000

Reexamination Certificate

active

06614701

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the testing of a semiconductor memory device, more specifically to a method for testing for the presence and correct working of charge-replacing circuitry commonly found in semiconductor memory cells.
BACKGROUND OF THE INVENTION
A large number of memory cells used in modern semiconductor memory arrays include pairs of transistors, cross-coupled to form bistable latches, as illustrated in FIG.
1
. Such memory cells have two nodes, N
1
and N
2
, represented by the drains of the respective transistors, hereafter referred to as storage transistors. By selectively coupling each node to a respective bit-line (“bit”, “notbit”) and then taking one bit-line high and the other low, potentials can be stored on each of the nodes. More specifically, the first bit-line “bit” connected to the first node N
1
may be taken high, thus taking the first node high, whilst the second bit-line “notbit”, connected to the second node N
2
is taken low, thus taking the second node low. It should be noted that for the bistable circuit to be in a stable state, the value stored on one node must be the logical opposite of that stored on the other node. An identical value on each node represents an unstable state.
In the following description, the convention is adopted wherein the value stored by the cell is taken to be the value stored on the first node N
1
. For example, if the cell has a high (sometimes referred to as a ‘1’) stored on the first node N
1
, and therefore a low (sometimes referred to as a ‘0’) stored on the second node N
2
, the cell may be taken to be storing a high. Using the opposite convention the same cell would be deemed to be storing a low.
If the nodes are subsequently disconnected from the bit-lines, the bistable latch circuit would ideally retain its state indefinitely. However, charge from the node storing the high may leak through the respective storage transistor to ground. This may be caused by defects in the manufacturing process used to make the circuits or may be the unavoidable result of the physics of the circuit. A common mode of leakage, other than a manufacturing defect, is charge leakage directly from the node to the ground terminal. This is due to the fact that the NMOS transistors commonly used in circuits of this type have sources and drains comprising N-type silicon which is fabricated in a P-type substrate. The NMOS sources and drains thus form P-N diodes with the substrate which are reverse biased during normal operation. These reverse biased diodes pass a small amount of current called “leakage current”. Should this occur, the cell will retain its contents for a period of milliseconds or seconds but then lose its state.
To ensure that the contents of the cell will not be lost if the cell is left for a long period of time, circuitry for replacing any charge lost due to leakage is normally incorporated into the cell. Circuitry is connected between a positive voltage supply and each node of the memory cell. As charge leaks from the node, it is replaced by charge flowing through the charge-replacing circuitry (hereafter identified as CRC) from the positive voltage supply.
FIG. 1
shows a basic memory cell having no CRC. Because of charge leakage, such a cell will have no ability to retain its state for a long period of time once it is isolated from the bit-lines. The cell consists of four transistors, M
1
, M
2
, M
4
and M
6
. M
4
and M
6
are the storage transistors and form the main body of the cell. Both have their sources connected to ground, and their gates and drains are cross coupled to form a bistable latch, with the drain of one connected to the gate of the other and vice versa. Nodes N
1
and N
2
correspond respectively to the drains of M
4
and M
6
and are connected, respectively, to bit-lines “bit” and “notbit” via access transistors M
1
and M
2
. Transistors M
1
and M
2
have the function of coupling, respectively, nodes N
1
and N
2
to bit-lines “bit” and “notbit” in response to an activating signal on word-line
10
. When the activating signal on word-line
10
is low, access transistors M
1
and M
2
are turned off, isolating the cell from bit-lines “bit” and “notbit”.
FIG. 2
shows a memory cell similar to that shown in
FIG. 1
, but which includes CRC for replacing charge lost due to leakage. This is a six-transistor static RAM cell. In this diagram, the main body of the cell consists of four transistors, M
3
-M
6
. Transistor M
4
has its drain connected to the gate of transistors M
5
and M
6
and to the drain of M
3
. Similarly, transistor M
6
has its drain connected to the gate of transistors M
3
and M
4
and the drain of transistor M
5
. As before, nodes N
1
and N
2
corresponding, respectively, to the drains of transistors M
4
and M
6
are coupled to bit-lines “bit” and “notbit” respectively via access transistors M
1
and M
2
which are activated in response to a signal on word-line
10
. M
3
and M
4
form an inverter, as do M
5
and M
6
. The inverters are cross-coupled so that the output of one inverter is the input of the other, forming a bistable latch. When the cell is isolated from the bit-lines “bit” and “notbit”, by turning off M
1
and M
2
, the main body of the cell will actively retain its state. Because the cell has active feedback through the inverters in the cell, any charge lost from N
1
or N
2
will be replaced by the CRC connected to that node.
FIG. 3
shows a similar cell to that shown in
FIG. 2
, but having CRC implemented as a high value resistance in series with the storage transistors. This is known as a four-transistor static RAM cell. In the circuit shown in
FIG. 3
, the high value resistance takes the form of a pair of semiconductor diodes connected to each node. These diodes are connected in back-to-back arrangement, that is to say one diode is forward biased with respect to the voltage supply while the other is reverse biased with respect to the voltage supply. Thus the current passed by the diode pair is limited to the reverse saturation current of the reverse biased diode. This current is usually sufficient to replenish any charge lost due to leakage. However, the reverse biased diodes represent an effective resistance of tera-ohms to giga-ohms. Thus, the current passed by them is very small and if the charge leakage from the cell is relatively high, such a current may not be great enough to counteract the leaking charge. Furthermore, the circuit shown in
FIG. 3
has the drawback that a pair of diode loads must be added to the cell, adding extra cost and complexity to the manufacturing process. Therefore, it is more common for the circuit of
FIG. 2
to be used.
Often a cell is combined with many other cells to form an array comprising a plurality of columns of such cells and a plurality of rows of such cells. In an array, the cells in a column are connected via common bit-lines to allow reading and writing. The cells in a row are connected via common word-lines. The use of a cell with no CRC would cause the memory cells to fail unless a refresh circuit were coupled to counteract the effect of charge leakage every few milliseconds. This periodical charge replacement is implemented in DRAM memory cells, as is known in the art. However, there are some cases when a DRAM memory cell is not suitable, and hence an SRAM memory cell is required. In this situation, CRC provides a convenient way of ensuring that memory cells retain their state for a long period of time, by continually replacing leaked charge.
It is useful to be able to determine if the elements of the cell are functioning correctly. One test to achieve this is called the Marinescu 17N test and involves writing patterns of ‘0’s and ‘1’s into the cell and then reading them back and verifying them. The write part of the procedure is accomplished as outlined hereinabove, but the read part of the procedure is carried out as follows. The cell is isolated by turning off the word-line. The bit-lines are then charged to the supply voltage and the word-line is turned back on, reconnecting th

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