Wavetable address cache to reduce accesses over a PCI bus

Details Wavetable address cache to reduce accesses over a PCI bus Wavetable address cache to reduce accesses over a PCI bus

1996-09-17

1999-11-16

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

711154, 711200, 711206, 711207, 711221, 710126, G06F 1200, G06F 1202, G06F 1210

Patent

active

059875844

ABSTRACT:
A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a sample page base address corresponding to a first part of a first address received from a digital signal processor (DSP). The generated sample page base address is then stored in a sample page base address cache which can be accessed by the DSP without accessing a PCI bus. The first part of the first address is compared to a first part of a second address. Provided that the first part of the first address and the first part of the second address are the same, the present invention combines a second portion of the second address sent from the DSP with the generated sample page base address stored in the sample page base address cache. In so doing, the present invention generates a complete address of a sample to be fetched without accessing the PCI bus.

REFERENCES:
patent: 4972338 (1990-11-01), Crawford et al.
patent: 5295253 (1994-03-01), Ducousso et al.
patent: 5321836 (1994-06-01), Crawford et al.
PCI Special Interest Group, "PCI Local Bus Specification Revision 2.1", p. ii, Jun. 1, 1995.

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