Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2000-05-09
2003-11-04
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C341S144000
Reexamination Certificate
active
06643823
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a waveform generating circuit and, in particular, relates to a circuit which is applied to a tester for a semiconductor integrated circuit or the like and generates plural kinds of waveforms by using stored information of a data memory.
Waveforms for testing are necessary in the field of a tester for a semiconductor integrated circuit or the like. In such a field, it is required to generate plural kinds of waveforms for testing.
FIG. 3
is a block diagram showing the configuration of a waveform generating circuit known as a prior art. The waveform generating circuit is formed by pattern memories (data memories)
201
,
203
and edge selectors
205
,
209
. The conventional circuit configuration is arranged in a manner that kinds (N-th power of 2) of waveforms capable of being represented is determined by data width (N bits) of the data stored in each of the pattern memories (
201
,
203
).
Each of the pattern memories
201
,
203
stores data of N-bits. The edge selectors
205
,
209
respectively input data
202
,
204
each having a data width of N-bits. The edge selectors
205
,
209
select edges in response to a timing edge
207
and a timing edge
211
to generate N-th power of 2 kinds of waveforms as output data
213
and output data
215
, respectively.
In a case of generating waveforms more than the kinds of waveforms capable of being represented by the data width (N bits), the kinds of waveforms can be increased if a waveform synthesizing circuit
219
show in
FIG. 3
, for example, is further provided so as to synthesize the output data. The waveform synthesizing circuit
219
serves as an OR gate which outputs an output waveform
217
on a basis of the logical sum of the output waveform
213
and the output waveform
215
. In this case, since the variation of the output waveform
215
is contained within the variation of the output waveform
217
, the output waveform
217
can not be utilized separately from the output waveform
215
.
For example, in a case of supplying waveforms to a plurality of pins of an integrated circuit, it may be sometimes recognized on a circuit designer side in advance that there are pins to which a waveform of a large number of bits is required to be supplied and other pins to which a waveform of a small number of bits may be supplied. Thus, it is desired that a large number of bits is inputted into the edge selector to increase the variation of the waveforms corresponding to the large number of bits and on the other hand that the waveforms corresponding to the small number of bits are also generated and utilized.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a waveform generating circuit which can increase the kinds of output waveforms without depending on the width of data stored in a data memory.
Another object of the invention is to provide a waveform generating circuit which can increase the kinds of output waveforms generated from one of two output data and can effectively utilize waveforms in a manner that the waveforms generated from the other of the two output data are not contained in the variation of the waveforms generated from the one of the two output data.
In order to attain the aforesaid objects, the waveform generating circuit according to the invention is characterized by including section (
105
) for unevenly distributing, in response to N bit data (
111
,
113
) stored in each of a plurality of data memories (
101
,
103
), total bit number (2n) of the N bit data stored in the plurality of data memories; and section (
107
,
109
) for generating waveforms on a basis of the data (
115
,
121
) of the total bit number thus distributed unevenly.
According to another aspect of the invention, the waveform generating circuit according to the invention includes a dividing section (
105
), a first waveform section (
107
) and a second waveform section (
109
). The dividing section (
105
) inputs two data (
111
,
113
) having same bit number and divides the total bit number (2N) of the two data thus inputted into two data on a basis of a setting value &agr;. The first waveform section (
107
) generates, in response to a first edge signal (
117
), one (
115
) of the two data obtained by dividing the total bit number as a first waveform (
119
). The second waveform section (
109
) generates, in response to a second edge signal (
123
), the other (
121
) of the two data obtained by dividing the total bit number as a second waveform (
125
).
In this case, the absolute value of the setting value (&agr;) is set to an integer equal to or less than the bit number (N) of each of the two input data (that is, |&agr;|≦N). Further, the total bit number (2N) is divided in the two data in a manner that each of the two data (N+&agr;, N−&agr;) obtained by dividing the total bit number is relative with respect to the setting value (&agr;).
According to the aforesaid configuration, the kinds of the waveform of one of the two output data can be increased and the waveform of the other of the two output data can be utilized.
REFERENCES:
patent: 5093845 (1992-03-01), Kondoh et al.
patent: 5182558 (1993-01-01), Mayo
patent: 5432797 (1995-07-01), Takano
patent: 5859605 (1999-01-01), Raghavan et al.
Ando Electric Co. Ltd.
Fish & Richardson P.C.
Tu Christine T.
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