Wave pipelined output circuit of synchronous memory device

Details Wave pipelined output circuit of synchronous memory device Wave pipelined output circuit of synchronous memory device

2006-08-16

2008-09-09

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S189120, C365S230030, C365S230050

Reexamination Certificate

active

07423927

ABSTRACT:
Provided is a wave pipelined output circuit of a synchronous memory device. In the wave pipelined output circuit, paths for transferring data in a high frequency mode of the synchronous memory device are separated from paths for transferring the data in a low frequency mode of the synchronous memory device. The number of registers included in data output paths in the high frequency mode is reduced and the number of control signals used for data input/output of the registers is also reduced. Consequently, loads of the data output paths in the high frequency mode are decreased to improve a high frequency operation and reduce the chip area of the output circuit.

REFERENCES:
patent: 5384737 (1995-01-01), Childs et al.
patent: 5933369 (1999-08-01), Johnson et al.
patent: 5978311 (1999-11-01), Wilford et al.
patent: 11-265581 (1999-09-01), None
patent: 1999-0086391 (1999-12-01), None

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