Electrical computers and digital data processing systems: input/ – Input/output data processing – Flow controlling
Reexamination Certificate
2001-12-04
2004-03-30
Perveen, Rehana (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Flow controlling
C710S033000, C710S035000, C711S100000, C370S229000
Reexamination Certificate
active
06715002
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method and network device of controlling data flow as part of data-based networks, and more particularly, to the controlling of data arranged as into and out of a FIFO memory to increase the bus and memory resource utilization.
BACKGROUND OF THE INVENTION
Data networks have become increasingly important in day-to-day activities and business applications. Most of these networks are a packet-switched network, such as the Internet, which uses a Transmission Control Protocol (TCP) and an Internet Protocol (IP), frequently referred to as TCP/IP. The Transmission Control Protocol manages the reliable reception and transmission of network traffic, while the Internet Protocol is responsible for routing to ensure that packets are sent to a correct destination.
In a typical network, a mesh of transmission links are provided, as well as switching nodes and end nodes. End nodes typically ensure that any packet is received and transmitted on the correct outgoing link to reach its destination. The switching nodes are typically referred to as packet switches, or routers, or intermediate systems. The sources and destinations in data traffic (the end nodes) can be referred to as hosts and end systems. These hosts and end systems typically are the personal computers, work stations and other terminals.
To help move information between computers, the open system interconnection (OSI) model has been developed. Each problem of moving information between computers is represented by a layer in the model, and thus, establishes a framework for standards. Two systems communicate only between layers in a protocol stack. However, it is desirable to communicate with a pure layer in the other system, and to achieve such results, information is exchanged by means of protocol data units (PDUs), also known as packets. The PDUs include headers that contain control information, such as addresses, as well as data. At a source, each layer adds its own header, as is well known to those skilled in the art. The seven layers, starting at the physical layer, include: (1) physical; (2) data link; (3) network; (4) transport; (5) session; (6) presentation; and (7) application layers.
The network systems typically use routers that can determine optimum paths, by using routing algorithms. The routers also switch packets arriving at an input port to an output port based on the routing path for each packet. The routing algorithms (or routing protocols) are used to initialize and maintain routing tables that consist of entries that point to a next router to send a packet with a given destination address. Typically, fixed costs are assigned to each link in the network and the cost reflects link bandwidth and/or costs. The least cost paths can be determined by a router after it exchanges network topology and link cost information with other routers.
The two lower layers, the physical and data link layers, are typically governed by a standard for local area networks developed by the IEEE 802 Committee. The data link layer is typically divided into two sublayers, the logical link control (LLC) sublayer, which defines functions such as framing, flow control, error control and addressing. The LLC protocol is a modification of the HDLC protocol. A medium access control (MAC) sublayer controls transmission access to a common medium.
High-level data link control (HDLC) is a communications control procedure for checking the accuracy of data transfer operations between remote devices, in which data is transferred in units known as frames, and in which procedures exist for checking the sequence of frames, and for detecting errors due to bits being lost or inverted during transfer operations. There are also functions which control the set-up and termination of the data link. In HDLC, the bit synchronous data communication across a transmission link is controlled. HDLC is included in the ITU packet-switching interface standard known as X.25.
Programmable HDLC protocol controllers are commonly used in these systems. An HDLC controller is a computer peripheral-interface device which supports the International Standards Organization (ISO) high-level-data-link-control (HDLC). It reduces the central processing unit or microprocessor unit (MPU) software by supporting a frame-level instruction set and by hardware implementation of the low-level tasks associated with frame assembly-disassembly and data integrity.
Most communication protocols are bit-oriented, code-dependent, and ideal for full duplex communication. Some common applications include terminal-to-terminal, terminal-to-MPU, MPU-to-MPU, satellite communication, packet switching, and other high-speed data links.
A communication controller relieves a central MPU of many of the tasks associated with constructing and receiving frames. A frame (sometimes referred to as a packet) is a single communication element which can be used for both link-control and data-transfer purposes.
Most controllers include a direct memory access (DMA) device or function which provides access to an external shared memory resource. The controller allows either DMA or non-DMA data transfers. The controller accepts a command from the MPU, executes the command, and provides an interrupt and result back to the MPU.
Typically, many routers or HDLC controllers or other similar controllers include separate FIFO memory structures to provide independent transmit and receive buffering. A standard or classic method of FIFO flow-control is an interrupt-mediated system based upon watermark settings in the FIFO. For example, when the receive watermark is toggled by incoming data off the network, an interrupt signal is issued to the embedded microprocessor core. The DMA is then instructed by the frameware or the state machine to read a predefined quantity of data from the receive FIFO. In this way, frames are received from the network without overflowing the receive FIFO memory.
Conversely, when the standard transmit FIFO watermark is satisfied, the transmit FIFO memory and its associated logic control circuits initiate an interrupt signal indicating that sufficient space exists within the FIFO memory for it to receive a data burst from the direct memory access unit (DMA). The service time for either receive or transmit interrupt is delayed based upon a function of their respective interrupt priority assignments (low, medium, high) and their relative position in the microprocessor interrupt stack.
Once the interrupt has initiated the burst request of the DMA, it generally exits to allow any central processing unit to serve the next process. The number of system clocks required to generated this DMA command can be relatively high. A typical controller of this type spends most of its processor time deciding which command it needs to build, building it, and then submitting the command to the DMA command stack for execution.
Because the write rate into the transmit FIFO is generally much faster than the output rate of the FIFO to the network because of various factors, such as contending for a host bus and other similar reasons, most network devices depend entirely on their standard watermark settings for indications when a DMA burst is required. Although this does have some advantages, it also has disadvantages.
For example, performance could be wasted if either the burst is small or the watermark is too large. If the network device supports multiple channels, it may also be time-slicing between the various channels and suffering additional overhead because of interrupt servicing. Both receive and transmit FIFOs are susceptible to packet corruption. If the DMA fails to read data out of the receive FIFO faster than its input rate, it risks an overflow error and the loss of one or more packets. Similarly, if the DMA is unable to write a complete packet into the transmit FIFO to keep up with the output rate, it runs the risk of an under-flow error. If the firmware within a processor writes too much information into the FIFO, a transmit overflow results. Additionally, different overhe
Jorgenson Lisa K.
Perveen Rehana
Regan Christopher F.
STMicroelectronics Inc.
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