Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data... – Inhibiting timing generator or component
Reexamination Certificate
1996-07-26
2002-04-23
Courtenay, III, St. John (Department: 2151)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
Inhibiting timing generator or component
Reexamination Certificate
active
06378083
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a watch dog timer device used for a microprocessor system, and, in particular, to a watch dog timer device for use in a highly reliable microprocessor system having a system but master other than a Central Processing Unit (CPU) such as a Direct Memory Access Controller (DMAC), a Dynamic Random Access Memory (DMAC) refresh (RAS only), and the like. The invention allows for the detection of program runaway.
2. Description of the Prior Art
Conventionally, a function for resetting a system is adopted to detect an occurrence of a program runaway in order to increase the reliability of a system containing a CPU. A watchdog timer is normally used for this purpose.
The watchdog timer sets a value on a preset timer for a time period which is a time-out from a program runaway, and acts to implement a normal timer clearance within the range of the set value by a CPU instruction. In the case where the program is functioning normally under set conditions of this type, before the timing of a time-out detected by the timer, the timer is cleared by the CPU so that the system is considered to operate normally.
As opposed to this, in the case where a timer clearance for the timer has not been executed by a CPU instruction but is mainly caused by an abnormality such as a program runaway or the like, the watch dog timer which has not been cleared overflows from a time-out. Specifically, an abnormal signal is generated by the watch dog timer corresponding to an abnormal operation such as a program runaway, and an overflow signal is transmitted to a CPU and other external devices. The system is optionally reset using this overflow signal from the watch dog timer device, or a non-maskable interrupt (NMI) process or the like is carried out, so that the system is finally returned to a normal operational state.
There is a microprocessor system including a bus master such as a DMAC or the like. In this type of the system the CPU in the system cannot clear a time period set in the watch dog timer device during the operation of the DMAC. For this reason, the existence of a bus master such as a DMAC or the like in a microprocessor system has a large influence on the use of a watch dog timer. Specifically, while the DMAC uses the bus for a direct memory access operation for internal and external memories such as, for example, a cache memory, external hard disk drives, and the like, it is not possible to provide a clearance signal in order to reset the time period of the watch dog timer through the bus from the CPU. Therefore a time period occurs in which the watch dog timer cannot be cleared. Avoiding this problem requires an appreciable amount of restrictions on the microprocessor system in operation and hardware. In general, it is impossible to avoid these restrictions.
In order to avoid these restrictions when a watch dog timer device is incorporated in the conventional microprocessor system, for example, when a bus master such as a DMAC or the like is present in a microprocessor system, an interrupt operation is required prior to a commencement of a DMA operation so that the watch dog timer does not operate.
FIG. 1
is a block diagram of a conventional microprocessor system incorporating a conventional watch dog timer device. As illustrated in
FIG. 1
, a CPU
1
, a runaway detection circuit
2
, and a DMAC
3
are connected to a control bus
6
. A transmission request holding circuit
4
is connected to the DMAC
3
. The CPU
1
has a function for releasing use of the control bus
6
to other devices. The runaway detection circuit
2
has a configuration including a watch dog timer with a program runaway detection function. The runaway detection circuit
2
receives a timer clearance signal from the CPU
1
prior to the time-out, but when the timer has not been cleared from whatever cause, the runaway detection circuit
2
overflows at the timing of the time out, and a Watch Dog Time Out signal (WDT OUT) S
3
is transmitted to the CPU
1
, the DMAC
3
, and the other circuits through a special-purpose lines SPL.
The DMAC
3
has a request function for the right to use the control bus
6
. The direct memory access controller DMAC
3
receives a Direct Memory Access (DMA) transmission request S
2
from the transmission request storage circuit
4
and a bus request S
4
is transferred to the CPU
1
, while a bus permission signal S
5
is received from the CPU
1
.
FIG. 2
shows a configuration of the transmission request storage circuit
4
.
The transmission request storage circuit
4
monitors the prohibition or approval state of the runaway detection circuit
2
by means of a DMA transmission request S
1
, and has the function of storing the DMA transmission request.
Specifically, as shown in
FIG. 2
, the DMA transmission request signal S
1
is transmitted to a terminal A of the transmission request storage circuit
4
, and a port output (DMA permission signal S
7
is transmitted to a terminal D of the transmission request storage circuit
4
from the CPU
1
. An interrupt request signal S
6
is transmitted from a terminal C in the transmission request storage circuit
4
to the CPU
1
and the DMA transmission request signal S
2
is transmitted from a terminal B in the transmission request storage circuit
4
to the DMAC
3
.
The DMA transmission request signal Si received at the terminal A and the port output (DMA permission signal) S
7
received at the terminal D are provided together to logic circuits
8
,
10
, and
11
in the transmission request storage circuit
4
.
The DMA transmission request signal S
2
is transmitted from a logic circuit
11
through the terminal B to the DMAC
3
. In addition, the output from the logic circuits
8
and
10
are transmitted through a logic circuit
9
and the terminal C to the CPU
1
as the interrupt request signal S
6
.
In the above-described configuration of the transmission request storage circuit
4
shown in
FIG. 2
, a timer clearance signal or a timer reset signal is received from the CPU
1
via the control bus
6
during normal operation so that there is no time-out in the runaway detection circuit
2
. However, the program runs away from some cause, and there is no timer reset signal from the CPU
1
to the runaway detection circuit
2
. In this case, the runaway detection circuit
2
enters an overflow state as a result of the time-out, and transmits a Watch Dog Time OUT (WDTOUT) signal S
3
for use of a reset operation to the runaway detection circuit itself
2
, the CPU
1
, the DMAC
3
, and external devices (not shown) through special purpose lines.
Next, the operation of the DMAC
3
will be explained with reference to the timing chart shown in FIG.
3
. In
FIG. 3
the letter (A) designates the state of the DMA transmission request signal S
1
, (B) designates the state of the DMA transmission request signal S
2
, (C) designates the state of the interrupt request signal S
6
, (D) designates the state of the port output (DMA permission signal) S
7
, and (E) designates the state of the bus cycle of the control bus
6
.
First, at a time t
1
at which the control bus
6
is in a normal cycle condition, the DMA transmission request signal S
1
changes from a high level (H level) to a low level (L level). In this case, the DMA transmission request signal S
1
is transmitted to the transmission request storage circuit
4
from external devices. At this time the interrupt request S
6
is transmitted from the transmission request storage circuit
4
to the CPU
1
. On receipt of this interrupt request S
6
, the CPU
1
processes an interrupt operation during from a time t
2
to a time t
4
, and prohibits operation of the runaway detection circuit
2
. At a time t
3
after this interrupt operation has been completed, the port output (DMA permission signal) S
7
is returned from the CPU
1
to the transmission request storage circuit
4
. As a result, the DMA transmission request signal S
2
is transmitted from the transmission request storage circuit
4
to the DMA
Hinata Seiji
Yamanaka Hideki
Courtenay III St. John
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
LandOfFree
Watch dog timer device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Watch dog timer device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Watch dog timer device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2885857