Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1998-09-23
2001-02-27
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000, C438S121000
Reexamination Certificate
active
06194247
ABSTRACT:
BACKGROUND OF THE INVENTION
A. Field of the Invention
This invention relates to a method for fabricating warp-resistant ultra-thin integrated circuit packages. In particular, the invention relates to reducing the thickness of the layers of the integrated circuit package and mounting thin layers of material to the upper and lower major surfaces of the integrated circuit package to prevent thermal and mechanical warping.
B. Discussion of the Related Technology
Packaging techniques for integrated circuits have been developed in the past in an attempt to satisfy demands for miniaturization in the semiconductor industry. Improved methods for miniaturization of integrated circuits enabling the integration of millions of transistor circuit elements into single integrated silicon embodied circuits, or chips, have resulted in increased emphasis on methods to package these circuits in space efficient, yet reliable and mass-producible packages.
The introduction of highly sophisticated integrated circuit computers and other common bus systems utilizing a variety of integrated circuit elements such as memory devices (DRAMs, VRAMs, FLASH ROMs, E-ROMs, and SRMs), programmable logic arrays (PLAs), microprocessors (CPUs), coprocessors, and other related integrated circuit elements which had to be assembled, mounted and interconnected into as compact, yet reliable packages as feasible to satisfy the industry demands for miniaturization.
Other key considerations in developing packaging for such circuits have been the cost of manufacture, the reliability of the packaged device, heat transfer, moisture penetration, standardization of mounting and interconnect methods and the ability to test and control the quality of the packaged devices.
In the past, one area of concentration for high density packaging has been memory devices such as SRAMs and DRAMs. Prior systems typically utilized a transfer molded plastic encasement surrounding the integrated circuit and having one of a variety of pin-out or mounting and interconnect schemes. The older M-DIPs (Dual-In-Line-Plastic) provides a relatively flat, molded package having dual parallel rows of leads extending from the bottom for through-hole connection and mounted to an underlying circuit board substrate. These packages provided
100
mil spacing between leads.
A more dense package was the 100 mil SIP (Single-In-Line-Plastic), which was assembled on edge with two rows of 100 mil staggered leads extending from the bottom edge for through-hole assembly. Another popular prior art package is the PLCC (Plastic Leaded Chip Carrier), SOJ (Small Outline J-leaded) molded package with twenty surface-mount designed J-leads (length 0.67″, width 0.34″, height 0.14″).
Higher density versions of the SIMM (Single-In-Line Memory Module) design with even smaller versions of the DRAM plastic package have been developed. These thinner versions of SOJ DRAMs are one-half the thickness (having a plastic packaging thickness of about 70 mils) of standard SOJ designs, and have been mounted on both sides of circuit board substrates. Even smaller TSOP (Thin Small Outline Package) packages have been developed experimentally with a plastic thickness of 1 millimeter and lower profile gull-wing leads for surface mounting. Based on experience with these prior art designs, for reasons of reliability related to moisture penetration and mechanical integrity, the industry has adopted a standard thickness for plastic packaging of approximately 1 millimeter (40 mils), or approximately 10.5 mils on each side of an 11 mil thick integrated circuit element attached to a 6 mil thick lead frame.
In an attempt to configure electronic systems in ever smaller packages, new methods and apparatus comprising three-dimensional stacked integrated circuit packages have been developed as more fully described in U.S. patent application Ser. Nos. 07/561,417 and 07/884,066, filed Aug. 1, 1990 and May 15, 1992, respectively, both having the common assignee of the present invention and incorporated herein by reference for all purposes. Such multiple package modules pose an even greater need for heat dissipation.
An example of a fabrication method and apparatus for lead-on chip integrated circuits having improved thermal dissipation characteristics is more fully described in co-pending U.S. patent application Ser. No. 07/746,268, filed Aug. 15, 1991, Patent Cooperative Treaty International Application No. PCT/US92/06778, and U.S. patent application Ser. No. 07/783,737, filed on Oct. 28, 1991, each having the common assignee of the present invention and incorporated herein by reference for all purposes. There are integrated circuit packages in commercial production, such as, for example, the TSOP type whose thermal transfer characteristics could be improved upon after manufacture by modifying such packages in accordance with the present invention, thus allowing greater integrated circuit packaging densities and improved reliability.
An example of a fabrication method and apparatus for high density lead-on-packages achieved by laminating one or more lead frames to a standard integrated circuit package is more fully described in co-pending U.S. patent application Ser. No. 07/990,334, filed Dec. 11, 1992, having the common assignee of the present invention and incorporated herein by reference for all purposes. This co-pending U.S. patent application Ser. No. 07/990,334 discloses the use of a stiffener to prevent the warping of a thin integrated circuit package, but this stiffener provides resistance only to mechanical warpage.
In contrast to such prior art technology, the fabrication method of the present invention provides warp-resistant ultra-thin integrated circuit packages that are thermally and mechanically balanced to prevent the ultra-thin profile packages from warping.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating modified integrated circuit packages from standard integrated circuit packages to provide enhanced thermal conductivity. Achieving improved thermal transfer characteristics from an integrated circuit package results in better heat dissipation and more reliable operation. Using standard commercially-available integrated circuit packages, such as TSOP, allows economical and rapid fabrication of thermally and electrically superior electronic circuits for applications that demand high reliability and performance. Furthermore, the modification provided by the present invention greatly facilitates use of the modified package in a multi-unit, stacked three-dimensional module by providing warp-resistant ultra-thin integrated circuit chip packages so the module will take up less space.
In order to achieve the thinnest package possible, all fabrication layers needed to construct a useful integrated circuit package must be minimized in thickness and number. The present invention discloses an ultra-thin integrated circuit package, which results from reducing the number of layers and the thickness of each layer to a minimum during fabrication of the package elements.
An integrated circuit package contains an integrated circuit die attached to an internal lead frame, which are encapsulated with materials such as transfer-molded plastic. A feature of the present invention is to make the integrated circuit package thinner by lapping or grinding off some of the casing material. A thinner integrated circuit package, however, may warp during fabrication or use due to dissimilar coefficients of thermal expansion in the various layers or component parts which comprise the package. To prevent warping while still maintaining a thin profile, a thin layer of material with a coefficient of thermal expansion that is equal to or less than the coefficient of thermal expansion of silicon is mounted to the upper major surface of the integrated circuit package after the upper major surface has been made thinner by lapping or grinding off some of the casing material uniformly. A suitable material with a coefficient of thermal expansion less than that of silicon that is mounted
Burns Carmen D.
Cady James W.
Roane Jerry M.
Troetschel Phillip Randall
Collins D. M.
Denko J. Scott
George & Donaldson, L.L.P.
Picardat Kevin M.
Staktek Group L.P.
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