Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1999-12-23
2003-05-13
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
Reexamination Certificate
active
06564330
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains generally to a power control circuit. More particularly, it pertains to a wake up circuit for a computer system with a codec.
2. Description of the Related Art
A number of methods have been developed for reducing power consumption in a computer system by shutting down various portions of the system. This is commonly done by putting one or more selected circuits into a sleep mode from which the circuits may be awakened. Sleep modes can involve shutting off power to a circuit, but are more commonly implemented by leaving power on and stopping all clock activity, which reduces power consumption significantly and has the advantage of preserving context information. Industry standards have been developed to define various levels of sleep states. Sleep states for devices are defined by states D
0
through D
3
, where D
0
is fully active and operational, and D
3
is completely off with no preservation of context information. Sleep states for computer systems are defined by states S
0
through S
5
, where S
0
is fully operational, and S
5
is completely off with no preservation of context information. Systems and their connected devices can be put into sleep states independently. A device that is not being used can be put into a sleep state while the system continues to operate. Alternately, a system with no current tasks to perform can be put into a sleep state, but the devices that are supposed to detect wake events must remain at least partially active so that they can detect those events and trigger a wakeup sequence in the system.
Many areas of computer technology have well developed sleep/wakeup provisions. An area that is not well developed, however, is the area of codec interfaces. One common codec design separates the analog functions from the digital functions by defining analog codecs connected over a bus link to a digital codec controller. Sleep modes for the codecs are well defined, allowing these peripheral areas to be shut down for power saving and reawakened by the system as needed. If there is no codec activity, the codec bus can also be shut down. However, if the system itself is put into a sleep mode, a codec that detects a wakeup event must convey a wakeup signal to the system, whether the codec bus is active or not. In conventional systems, there is no satisfactory process defined for generating a wakeup signal under both conditions.
FIG. 1
shows a block diagram of a conventional system
1
, having a single digital controller
10
controlling primary codec
11
and secondary codec
12
, and with provisions for up to four codecs per controller. Controller
10
can interface with a processor system over bus
30
. After being set up by the processor, controller
10
acts as a direct memory access (DMA) controller, transferring codec data directly to and from memory without further intervention by the processor. Four of the interconnecting lines on bus link
19
are shared, while each codec has its own individual DATA_IN line for data inputs to the controller. Primary codec
11
outputs a bit clock on line
14
, which is used to synchronize signal transitions on all the other lines of link
19
. The SYNC signal on line
13
is used to define the start of data frames. As long as BIT_CLK is active, SYNC will be active and bus link
19
is considered active. Controller
10
can direct primary codec
11
to stop the bit clock, thus putting the bus into a sleep state. Under this condition, any codec can request a bus activation by raising its DATA_IN line and keeping it high, which causes controller
10
to generate a power management signal to the system so that a system wakeup sequence can be started. Once the system becomes operational, it directs the controller to generate a SYNC signal on the codec bus, which in turn causes the requesting codec to drop its DATA_IN line and causes the primary codec to resume the bit clock. Once the system and codec bus are both awake, the system can interact with the codec that initiated this sequence to determine what the wakeup event was and how to deal with it.
However, if the system is in a sleep mode but the codec bus is still active, raising the DATA_IN line does not trigger the above events, and there is no defined way for a codec to trigger the power management interrupt.
SUMMARY OF THE INVENTION
The invention includes a wakeup circuit with a data input for receiving a data input signal from a codec, a clock status input for receiving a clock status signal, and a device status input for receiving a device status signal. It also includes a wakeup status output for transmitting a wakeup status signal. The wakeup status signal is asserted if the device status signal is asserted. The wakeup status signal is also asserted if the clock status input signal is not asserted and the data input signal is asserted.
REFERENCES:
patent: 6263075 (2001-07-01), Fadavi-Ardekani et al.
patent: 6272645 (2001-08-01), Wang
patent: 6275947 (2001-08-01), Wang
patent: 6408351 (2002-06-01), Hamdi et al.
patent: 6408396 (2002-06-01), Forbes
“Intel 82801AA (ICH) & Intel 82801AB (ICH0) I/O Controller Hub AC '97, Programmers's Reference Manual”, Dec. 1999.*
INTEL Corporation, “Audio Codec '97”. Revision 2.1; May 22, 1998, pp 1-108.
Martinez Alberto J.
Poisner David I.
Vadivelu Karthi R.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Lee Thomas
Wang Albert
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