Static information storage and retrieval – Addressing – Multiple port access
Utility Patent
1999-02-04
2001-01-02
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Multiple port access
C365S233100, C365S189040, C365S230060
Utility Patent
active
06169700
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to dual port access to elements of a common device. More particularly, it relates to a wait state generator which allows simultaneous access to all elements of the common device, e.g., dual port memory.
2. Background of Related Art
Digital memory is found in nearly every digital electronic device, particularly when such device includes a processor (e.g., a microprocessor, microcontroller, or digital signal processor). Many types of digital memory exist, perhaps the most common form being random access memory (RAM).
With advancements in technology came the need to include more than one processor in a device. While each processor (or other) device has its own assigned tasks, information is typically made available to either processor through the use of a commonly accessible memory, e.g., RAM. This commonly accessible memory is typically called a “dual port memory” because it usually has an individual address and data bus (i.e., port) for each accessing processor.
Dual port memories are used in digital circuitry to allow two address/data buses access to common memory. For instance, a microprocessor and a digital signal processor may cooperatively pass data back and forth through the common memory. In such a case, the first processor or other device would access particular address/data locations using a first port of the dual port memory, and the second processor or other device would access particular address/data locations using a second port of the dual port memory.
FIG. 5
shows a conventional dual port, common memory
504
having a first port
579
including an address and data bus connected to a first processor
500
, and a second port
589
including another address and data bus connected to a second processor
502
.
As shown in
FIG. 6
, from an external perspective, it appears as if either processor
500
,
502
can access any memory location
530
-
545
at any time. For instance, in the example shown in
FIG. 6
, the first processor
500
is addressing memory location
535
, and the memory location
535
is allowing an appropriate write operation (or other operation) on the first data bus DATA 1 corresponding to the first processor
500
. At the same time, the second processor
502
is accessing memory location
542
using its corresponding address and data buses ADDR 2, DATA 2. The example of simultaneous access to memory locations
535
and
542
by the respective processors
500
,
502
using conventional dual port memory
504
operates correctly.
However, as shown in the example of
FIG. 7
, a collision would occur in the event that both processors
500
,
502
try to access the same memory location (or memory block commonly enabled)
542
. In this case, an unpredictable state would occur with respect to data output on the respective data buses DATA 1, DATA 2.
FIG. 8
shows a common solution to the problem of potential collisions in accesses to memory locations in conventional dual port memory.
In particular, in
FIG. 8
, a multiplexing scheme is implemented, e.g., using multiplexers
800
,
802
, together with an arbiter
840
. The arbiter allows singular access to the common memory
504
at any one time by alternately controlling a multiplexer relating to the address ports ADDR 1, ADDR 2, and a multiplexer relating to the data ports DATA 1, DATA 2. Only one address is applied to an address decoder
820
in the common memory
504
at any one time, thus enabling only one memory location
530
-
545
at any one time to output on either data bus DATA 1, DATA 2.
Multiplexed access to common memory locations from two ports prevents the potential for collisions between accesses by two processors or other devices utilizing the two ports of a dual port memory. However, because of the serial access to the common memory
504
, dual port memories often require more time than the maximum speed of the common memory
504
if it were a single port memory, i.e., accessed only from one processor without the use of the multiplexers
800
,
802
.
Another technique to prevent collisions in accesses to common memory is to synchronize the accesses of the two processors
500
-
502
to be not coincidental in time with one another.
An exemplary use of dual port memory is to provide a message box area to create a new way of real-time asynchronous inter-processor communications. Conventionally, as described, asynchronous processors typically communicate using common memory (e.g., RAM, a shared register, etc.) and a multiplexed address, under the control of hand-shaking and/or interrupt driven routines. Thus, access to the common memory space is separated in time between the two ports of the dual port memory to avoid collisions in accesses to particular locations in the common memory, particularly in write cycles from either processor. Unfortunately, this type of inter-processor communication is slow because, e.g., of the serial access to the memory locations by the two processors, and because of any additional time required to handle hand-shaking and/or interrupt routines.
There is thus a need for an efficient method and apparatus to allow simultaneous, asynchronous access to common elements in a common device, e.g., in a dual port memory or other dual port, addressable device.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a dual port addressable device comprises a first address decoder adapted to enable access to any of a plurality of addressed locations from a first data bus. A second address decoder is adapted to enable access to any of the plurality of addressed locations from a second data bus. A wait state generator is adapted to activate a wait state signal in response to an attempted simultaneous access to any one of the plurality of addressed locations.
A method of allowing simultaneous, asynchronous access from two ports to a common addressable location in accordance with another aspect of the present invention comprises decoding a first valid address on a first port. A second valid address is simultaneously decoded on the second port while the first valid address is being decoded on the first port. A wait state signal is generated to delay a second access on the second port based on the decoded second valid address until after a first access on the first port is completed.
REFERENCES:
patent: 5434989 (1995-07-01), Yamaguchi
patent: 5502683 (1996-03-01), Marchioro
patent: 5768211 (1998-06-01), Jones et al.
Bollman William H.
Hoang Huan
Lucent Technologies - Inc.
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