Wafer via formation

Details Wafer via formation Wafer via formation

2011-01-18

2011-01-18

Landau, Matthew C (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S668000, C257SE21597

Reexamination Certificate

active

07871927

ABSTRACT:
A method of electrically conductive via formation in a fully processed wafer involves defining at least one trench area on a backside of the fully processed wafer, forming at least one trench within the trench area to an overall depth that will allow for a via formed within the trench to be seeded over its full length, forming the via within the trench into the fully processed wafer to a predetermined depth, depositing a seed layer over the full length of the via, and plating the seed layer to fill the via with an electrically conductive metal.

REFERENCES:
patent: 3312878 (1967-04-01), Poch et al.
patent: 5037782 (1991-08-01), Nakamura et al.
patent: 5075253 (1991-12-01), Sliwa, Jr.
patent: 5100480 (1992-03-01), Hayafuju
patent: 5220530 (1993-06-01), Itoh
patent: 5229315 (1993-07-01), Jun et al.
patent: 5308784 (1994-05-01), Kim et al.
patent: 5399898 (1995-03-01), Rostoker
patent: 5563084 (1996-10-01), Ramm et al.
patent: 5587119 (1996-12-01), White
patent: 5608264 (1997-03-01), Gaul
patent: 5614743 (1997-03-01), Mochizuki
patent: 5708569 (1998-01-01), Howard et al.
patent: 5780776 (1998-07-01), Noda
patent: 5814889 (1998-09-01), Gaul
patent: 5872338 (1999-02-01), Lan et al.
patent: 5929524 (1999-07-01), Drynan et al.
patent: 5962922 (1999-10-01), Wang
patent: 5973396 (1999-10-01), Farnworth
patent: 6013551 (2000-01-01), Chen et al.
patent: 6037665 (2000-03-01), Miyazaki
patent: 6075710 (2000-06-01), Lau
patent: 6184066 (2001-02-01), Chino et al.
patent: 6215114 (2001-04-01), Yagi et al.
patent: 6314013 (2001-11-01), Ahn et al.
patent: 6316737 (2001-11-01), Evans et al.
patent: 6330145 (2001-12-01), Lepert et al.
patent: 6391770 (2002-05-01), Kosaki et al.
patent: 6498089 (2002-12-01), Komada
patent: 6498387 (2002-12-01), Yang
patent: 6559540 (2003-05-01), Kawashima
patent: 6577013 (2003-06-01), Glenn et al.
patent: 6590278 (2003-07-01), Behun et al.
patent: 6599778 (2003-07-01), Pogge et al.
patent: 6706554 (2004-03-01), Ogura
patent: 6740576 (2004-05-01), Lin et al.
patent: 6770822 (2004-08-01), Pasternak et al.
patent: 6790775 (2004-09-01), Fartash
patent: 6887792 (2005-05-01), Perlov et al.
patent: 6939789 (2005-09-01), Huang et al.
patent: 7157310 (2007-01-01), Benson et al.
patent: 2001/0001292 (2001-05-01), Bertin et al.
patent: 2001/0033509 (2001-10-01), Ahn et al.
patent: 2001/0048166 (2001-12-01), Miyazaki
patent: 2002/0017399 (2002-02-01), Chang et al.
patent: 2002/0027441 (2002-03-01), Akram et al.
patent: 2002/0053726 (2002-05-01), Mikubo et al.
patent: 2002/0094675 (2002-07-01), Kerr et al.
patent: 2002/0102835 (2002-08-01), Stucchi et al.
patent: 2002/0127761 (2002-09-01), Mottura et al.
patent: 2002/0134581 (2002-09-01), Figueroa et al.
patent: 2003/0032278 (2003-02-01), Chen et al.
patent: 2003/0047799 (2003-03-01), Cheever et al.
patent: 2003/0052324 (2003-03-01), Kimura
patent: 2003/0071272 (2003-04-01), Faska et al.
patent: 2003/0080408 (2003-05-01), Farnworth et al.
patent: 2003/0085471 (2003-05-01), Iijima et al.
patent: 2003/0159262 (2003-08-01), Pasternak et al.
patent: 2003/0183943 (2003-10-01), Swan et al.
patent: 2003/0206680 (2003-11-01), Bakir et al.
patent: 2003/0232488 (2003-12-01), Chua et al.
patent: 2004/0016942 (2004-01-01), Miyazawa et al.
patent: 2004/0051168 (2004-03-01), Arai et al.
patent: 2004/0124523 (2004-07-01), Poo et al.
patent: 2004/0207061 (2004-10-01), Farrar et al.
patent: 2004/0219763 (2004-11-01), Kim et al.
patent: 2004/0256686 (2004-12-01), Sassolini et al.
patent: 2004/0262635 (2004-12-01), Lee
patent: 2005/0046034 (2005-03-01), Farrar
patent: 2005/0104027 (2005-05-01), Lazarev
patent: 2005/0104219 (2005-05-01), Matsui
patent: 2005/0121768 (2005-06-01), Edelstein et al.
patent: 2005/0146049 (2005-07-01), Kripesh et al.
patent: 2005/0164490 (2005-07-01), Morrow et al.
patent: 2006/0003578 (2006-01-01), Lee et al.
patent: 2006/0042952 (2006-03-01), Oliver et al.
patent: 2006/0046471 (2006-03-01), Kirby et al.
patent: 2006/0234443 (2006-10-01), Yang et al.
patent: 2006/0292854 (2006-12-01), Wang
patent: 2008/0006938 (2008-01-01), Patti et al.
patent: 2008/0020488 (2008-01-01), Clevenger et al.
patent: 0 516 866 (1992-12-01), None
patent: 0 757 386 (1997-02-01), None
patent: 1 415 950 (2004-05-01), None
Topol, A.W. et al., “Enabling Technologies for Wafer-Level Bonding of 3D MEMS and Integrated Circuit Structures”, Electronic Components and Technology Conference, 2004, vol. 1, Jun. 1-4, 2004, pp. 931-938.
International Search Report , PCT/US06/23364, dated Nov. 13, 2006.
International Search Report, PCT/US06/23366, dated Dec. 8, 2006.
International Search Report, PCT/US06/23297, dated Jan. 3, 2007.
International Search Report, PCT/US06/23249, dated Jun. 11, 2007.
International Search Report, PCT/US06/23361, dated Sep. 19, 2007.
International Search Report and Written Opinion for PCT/US2007/81380 mailed on Mar. 17, 2008.
International Preliminary Report on Patentability for PCT/US2007/081380 issued Apr. 22, 2009.
Extended European Search Report issued in European Patent Application No. 07844296.9 and dated Jun. 30, 2010.
First Office Action issued in Chinese Patent Application No. 2007800375496 and issued Aug. 10, 2010.

Affiliated with

Also associated with

Rating

Wafer via formation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer via formation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer via formation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2743881