Wafer translator having metallization pattern providing high...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C324S765010, C439S068000

Reexamination Certificate

active

07579852

ABSTRACT:
A metallization pattern for a wafer translator provides a high density layout of interdigitated contact pads, suitable for component placement, along with larger contact pads suitable for connection to external equipment terminals. In another aspect, electrically conductive material may be added to, or removed from, the high density layout of interdigitated contact pads and larger contact pads to modify, or reconfigure, the electrical pathways of the wafer translator.

REFERENCES:
patent: 4862077 (1989-08-01), Horel et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Wafer translator having metallization pattern providing high... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer translator having metallization pattern providing high..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer translator having metallization pattern providing high... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4093823

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.