Wafer thinning techniques

Details Wafer thinning techniques Wafer thinning techniques

2001-10-11

2004-07-20

Mills, Gregory (Department: 1763)

Adhesive bonding and miscellaneous chemical manufacture

Differential fluid etching apparatus

For liquid etchant

C156S345210, C156S345230, C156S345150

Reexamination Certificate

active

06764573

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor wafers, and more particularly to techniques for the simultaneous thinning of the backside surfaces of a plurality of semiconductor wafers using a non-crystallographic and uniform etching process.
2. Discussion of the Related Art
Semiconductors are generally defined as materials having an electrical conductivity intermediate between metals and insulators and are used in a wide variety of modern electronic devices. The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit are formed on a single wafer.
Generally, the process involves the creation of eight to 20 patterned layers on and into the substrate, ultimately forming the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface. While fabricating integrated circuits, it is commonplace to process both the front side and backside of the wafer.
Wafer thinning, more commonly known as backlapping, is generally carried out at the end of the device fabrication process in order to increase the fabricated wafer's thermal conductivity and to enhance signal transmission integrity across the device. Additionally, the wafer is thinned to facilitate correct operation of microwave or millimeter wave circuits. The wafer is normally thinned from the backside surface. A uniform (i.e., isotropic) etching process is generally needed to effectively thin the wafers to the desired final thickness.
In most cases, this involves reducing the wafer thickness from an initial 400-700 &mgr;m range down to a final range typically from 250 &mgr;m or less. In fact, current manufacturers of increasingly sophisticated and miniaturized electronic devices are demanding even thinner wafers, and therefore, 125 &mgr;m or less is now a fairly common final wafer thickness requirement. However, current mechanical (e.g., polishing), wet (e.g., chemical etch), and dry (e.g., plasma gas) thinning methods, even those capable of supposedly producing an acceptable final wafer thickness, do not provide good etch uniformity within an individual wafer, as well as good etch uniformity in a given batch of wafers (i.e., wafer-to-wafer uniformity). This lack of uniformity results in a high number of defective wafers that must be discarded, thus raising manufacturing costs and causing production delays.
Therefore, there is a need to develop techniques for thinning the backside surfaces of several wafers simultaneously to provide good etch uniformity within an individual wafer, as well as good etch uniformity in a given batch of wafers (i.e., wafer-to-wafer uniformity).
SUMMARY OF THE INVENTION
The present invention provides methods and apparatuses for the simultaneous thinning of the backside surfaces of a plurality of semiconductor wafers using a non-crystallographic and uniform etching process.
In accordance with the general teachings of the present invention, methods and apparatuses for simultaneously thinning the backside surfaces of a plurality of wafers comprised of a semiconductor material are provided.
The methods include the steps of (1) providing a fixture having a plurality of horizontally oriented receptacles for receiving the plurality of semiconductor wafers, (2) loading the plurality of semiconductor wafers into the plurality of receptacles, (3) providing an etchant solution capable of isotropically removing a layer of semiconductor material from the backside surface of the plurality of semiconductor wafers, and (4) immersing the loaded fixture into the etchant solution for a sufficient period of time to cause the removal of a layer of semiconductor material from the backside surface of the plurality of semiconductor wafers to form a plurality of thinned semiconductor wafers.
The apparatuses include (1) a fixture having a plurality of horizontally oriented receptacles for loading the plurality of semiconductor wafers therein, and (2) an etchant solution capable of isotropically removing a layer of semiconductor material from the backside surface of the plurality of semiconductor wafers, wherein when the loaded fixture is immersed into the etchant solution for a sufficient period of time a layer of semiconductor material is removed from the backside surface of the plurality of semiconductor wafers to form a plurality of thinned semiconductor wafers.
Additional objects, advantages, and features of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 4350553 (1982-09-01), Mendes
patent: 5976312 (1999-11-01), Shimizu et al.
patent: 6187515 (2001-02-01), Tran et al.
patent: 6203659 (2001-03-01), Shen et al.
patent: 6235147 (2001-05-01), Lee et al.

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