Static information storage and retrieval – Read/write circuit – Testing
Patent
1998-07-07
1998-11-24
Nelms, David
Static information storage and retrieval
Read/write circuit
Testing
365200, G11C 700
Patent
active
058417133
ABSTRACT:
On carrying out a wafer test for a plurality of semiconductor wafers, N in number, each having a plurality of chips, an initial wafer test is carried out for all of the semiconductor wafers to produce an initial wafer test result representing that each chip of each of the semiconductor wafers is any one of a good chip, a defective chip, and a predictive good chip which is predicted as the good chip if subjected to trimming. Subsequently, each of the predictive good chips is subjected to the trimming to be repaired as the good chips. After that, a final wafer test (8001-8012) is carried out for a reduced number M (M being a positive integer less than N) of sampled wafers sampled among the semiconductor wafers to produce a final wafer test result representing that each chip of each of the sampled wafers is any one of the good chip and the defective chip. The initial wafer test result for the semiconductor wafers except the sampled wafers is modified into a modified wafer test result for the semiconductor wafers except the sampled wafers so that each chip represented as the predictive good chip by the initial wafer test result is also represented as the good chip by the modified wafer test result. An entire wafer test result for all of the semiconductor wafers is produced by adding the modified wafer test result to the final wafer test result.
REFERENCES:
patent: 5399505 (1995-03-01), Dasse et al.
patent: 5581510 (1996-12-01), Furusho et al.
NEC Corporation
Nelms David
Phan Trong
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