Wafer scale or full wafer memory system, packaging method thereo

Details Wafer scale or full wafer memory system, packaging method thereo Wafer scale or full wafer memory system, packaging method thereo

1992-10-14

1994-05-03

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257401, 257391, H01L 2702, H01L 2710, H01L 2715

Patent

active

053090110

ABSTRACT:
To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.

REFERENCES:
patent: 4365319 (1982-12-01), Takemae
patent: 4380066 (1983-04-01), Spencer et al.
patent: 5072424 (1991-12-01), Brent et al.
"A 4-Mbit Full-Wafer ROM" Kitano et al., IEEE Journal of Solid-State Circuits, vol. SC-15 No. 4 Aug. 19 pp. 686-693.
Hewlett-Packard Journal, vol. 34, No. 8, Aug. 1983, PALO ALTO US-pp. 14-20 (LOB et al)-"High Performance VLSI Memory System", p. 14, right column line 10-p. 15 left column, line 15.

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