Wafer scale of full wafer memory system, packaging method thereo

Details Wafer scale of full wafer memory system, packaging method thereo Wafer scale of full wafer memory system, packaging method thereo

1990-12-13

1993-03-02

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

257730, 257731, H01L 2302, H01L 2312

Patent

active

051912244

ABSTRACT:
To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.

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