Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-20
2003-05-20
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
76, 76, 76
Reexamination Certificate
active
06567963
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This invention most generally relates to data transfer and broadband communication networks within a parallel computing system or a local area network. In particular, the present invention relates to wafer scale integration of optoelectronics.
2. Background of the Invention
Technological advancements have dramatically increased the capabilities and possibilities of computing electronics. The increased bandwidth and data transfer rates have resulted in commercial innovation and scientific advancements in many fields. However, data transfer continues to be a bottleneck. This is true for data transfer within an integrated circuit (IC), from one chip to another, from hybrid circuit to hybrid circuit, from integrated circuit board to another integrated circuit board, and from system to system.
Another driving factor leading to ever increasing demands for faster data transfer rates is the need to do tasks that are more complex, requiring multiple computing nodes to cooperate. Digital signal processing, image analysis, and communications technology all require a greater bandwidth. The demand for increased data transfer capability and greater bandwidth translates into increases in both the speed of the data transfer, and the amount of data that is transferred per unit time.
In general, the problems associated with data transfer within an IC and on a system network are similar. Increasing the data transfer rate can be done in any of several ways. Some increase in the data transfer rate can be obtained by increasing the speed at which signals are communicated from one part of a system or network to another. Presently, the fastest known transfer means is the use of optical signals that operate at the speed of light.
Another means to reduce system delays is to increase the bandwidth being used. In this approach, more information is sent at one time. Since the vast majority of systems and networks now are digital, the measure of the increase in bandwidth is in terms of the number of bits on a bus.
There are limitations to the available bandwidth, such as spacing and size requirements, noise problems, reliability of connectors, processing times, buffer size, and the power required to drive multiple lines off-chip. Increasing the transmission speed also has some limitations, as increasing the speed also increases power requirements, introduces timing skew problems across a channel, and usually requires more exotic processing than is standard practice. Combining higher transmission speeds and more bandwidth is exceedingly difficult and impractical.
Whether transferring data within a circuit or connecting system to system, the limited bandwidth of conventional hardware does not satisfy the marketplace. For high data rate transmissions, only fiber optics transmit data at Gigabit data rates. Fiber optic communication systems allow information to be transmitted by means of binary digital transmission. The data or information that is to be transmitted is converted into a stream of light pulses, wherein the presence of a pulse corresponds to the transmission of a binary “one,” and the absence of light corresponds to the transmission of a binary “zero.” An optical receiver is used to convert the stream of light pulses into an electrical signal that is processed to determine the transmitted information.
Typically the optical transmitters are light emitting devices such as vertical cavity surface emitting lasers (VCSELS) and light detecting devices such as photodiodes. The optical transmitters and receivers may be encompassed in a separate chip or fabricated on the same substrate and with accompanying electronics. The fabrication process is well known in the art and U.S. Pat. No. 5,978,401 provides background materials, and is incorporated by reference.
The transmitters have driver circuitry that drives the VCSELS, while the receivers also have receiver circuitry for processing the received signals. The transmitter driver circuitry and the receiver driver circuitry is usually in the form of ASIC devices. The combination of the VCSELS and photodiodes along with the ASIC driver circuitry is called an optical transceiver. One embodiment for hybridization of the transceiver elements is via flip-chip bonding, which is generally explained in U.S. Pat. No. 5,858,814, incorporated by reference herein.
Optical fibers are used to transmit the optical data off the transceiver device and the fibers mate with the transceiver for data transfer. A spacing problem exists when there are large arrays of transceivers and corresponding optic cables mating to each emitter and detector. The coupling and alignment of these multiple fiber optic cables is exceedingly difficult and there is a high defect rate in large bundles.
In particular, data transfer in and out of a processor is a major concern. If the memory resides off the chip and is connected by traditional electronic means, data access is particularly slow. Even if it is on the chip, the current capabilities of reticles limit the amount of memory that is possible to put on the chip.
In recent years, there has been increased interest in systems on a chip. The logical extension of this idea is the system on a wafer, so called wafer scale integration. There are advantages to integrating an entire system on a wafer. First, the entire mask set can be designed for a particular function, much like current microprocessors, but at a higher level. Second, the entire wafer experiences the same set of process conditions. Many circuits exhibit slight process dependencies such as shifts in threshold voltages in MOSFETs and it is advantageous for all of the MOSFETs in a system to exhibit the same sensitivities. A further benefit of wafer scale integration is that all of the elements of a circuit can be processed at the same time.
However, with existing wafer fabrication technology there are some severe constraints posed by the need to have circuit elements such as memory, and some supporting circuitry, physically close to the processor section of a chip. The reason for this requirement is that as the distance between circuit elements increases, so does the signal propagation delays. The signal propagation increases the delay associated with transferring data to and from memory, and the need to accommodate current interconnection schemes. To account for the additional signal delay it becomes necessary to slow the data rate into and out of memory.
A prior art example of the spatial relationship between the processor section and the memory is shown in FIG.
1
. The central processing unit (CPU)
10
is located in some small portion of the chip
30
, while the memory cells
20
are located as near as possible in order to minimize distance and therein minimize propagation delays. It is apparent that only a certain quantity of memory devices may be located in close proximity to the CPU. Additional memory devices may be located at a greater distance on the chip or be located off chip. In either scenario, the increased distance translates into propagation delays.
An additional problem involved in wafer integration deals with the internal connections. The imaging process involved in forming integrated circuits must be done in a ‘step and repeat’ manner because of limitations in imaging extremely fine structures across a large area. In sum, there are challenges associated with reliably making connections from one portion of a wafer to another using conventional lithographic techniques if the distances are too great.
The factors that limit the transferal of data to and from processors on a wafer become even more acute as compared to system level impediments. Though transfer rates within a chip are quite high, the inter-chip data transfer rates are appreciably slower than the intra-chip data transfer rates. This problem is due, in part, to the limited area on the perimeter of integrated circuits, which traditionally contains the Input/Output (I/O) buffers needed to drive signals off-chip. Consequently, there is often a severe lim
Maine & Asmus
Siek Vuthe
Tat Binh
Tera Connect Inc.
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