Static information storage and retrieval – Read/write circuit
Patent
1987-03-12
1991-12-10
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
36523003, 365236, 365239, G11C 700, G11C 800
Patent
active
050724240
DESCRIPTION:
DESCRIPTION
FIG. 1 shows some of the modules 10 on a wafer which may contain a few hundred modules arranged on the wafer. The modules are set in a grid of global lines, namely a V.sub.DD power line 11, a V.sub.SS power line 12, a WCK (wafer clock) line 13 and a CMND (command) line 14. All these lines go to bondsites on the edge of the wafer or WCK and CMND may go to a command module on the wafer.
FIG. 2 shows the same modules 10 minus the global lines but with inter-module lines 15 for transmit paths. Data may be sent through a chain of modules, starting at a bondsite identified as XMIT (transmit; not shown). The modules have four connections into their XMIT path and these connections are identified as follows: XIN terminal.
The modules have four connections out from their XMIT paths and these connections are identified as follows:
Unlike the XIN lines, these output lines are switched so that a module can select only one of its edge neighbours as the next module in the chain, on to which XMIT data is passed.
The modules are also connected by receive path inter-module lines 16 (FIG. 3) which allow data to be sent back to a bondsite identified as RECV (not shown).
The modules have four connections into their RECV paths:
These connections are switched in correspondence with XOUT connections.
The modules have four connections out of their RECV paths:
These connections branch, without switching, from an OUT terminal, so that return data is broadcast to all four neighbours, only one of which will have been set up to receive it.
The XOUT and RIN selections are effected by four selection signals SELN, SELE, SELS and SELW, whose generation is explained below. Only one of these signals can be true. If SELN is true, for example, the module routes the XMIT path to the adjacent module above and accepts RECV data from that module.
The SEL signals of the modules are set up basically as described in GB 1 377 859. Modules are added one by one to the chain, tested and retained if good, and the procedure is reiterated to grow a chain of interconnected modules. The chain tends to spiral in to the center of the wafer in the case of a peripheral bondsite for XMIT and RECV. There may be a plurality of such bondsites, say four, to improve the chance of finding a good place to start the chain. The testing is effected in stages in the present system, as described further below.
FIG. 4 illustrates a peripheral fragment 17 of a wafer with modules 10 and the bondsite terminals XMIT and RECV. Portions of the XMIT path and RECV path are shown in full and broken lines respectively, as they would be grown through modules in accordance with the algorithm that each module tries its selection options in the order SELN, SELE, SELS and SELW. The first module M1 fails with SELN (there is no module above it) but succeeds with SELE, so adding M2 to the chain. M2 succeeds with SELN and adds M3. M3 fails with SELN but succeeds with SELE, to add M4. M5 succeeds with SELN to add M5, and so on. In the example shown all modules are good, at least so far as their control logic is concerned.
Before turning to a full description of a module 10, a brief summary of the way in which it operates will be given. Normally the module merely acts as a link in the chain and outbound data and commands pass from XMIT through the XMIT path in the module with a 1-bit delay through each module. Inbound data returns to RECV through the RECV path in the module, also with a 1-bit delay through each module. Each module contains a 16 k.times.1 bit dynamic RAM unit which is constantly refreshed under control of a free-running address counter. The module also contains control logic which can respond to commands to effect SELN, SELE, SELS and SELW and to other commands of which the most important are READ and WRITE. When a module receives either of these commands, the chain is broken at that module and the RAM unit is written to in the case of WRITE and read from in the case of READ. Although the RAM unit is composed of random access blocks it is only addressed by the free running counter a
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patent: 3913072 (1975-10-01), Catt
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patent: 4493055 (1985-01-01), Osman
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IBM Technical Disclosure Bulletin, vol. 13, No. 8, Jan. 1971 (New York, US), R. Veit: "Increased packing density of monolithic storages", p. 2436.
Patents Abstracts of Japan, vol. 2, No. 156 (10217) (E-78), 26 Dec. 1978, and JP, A, 53-126229 (Nippon Denki K.K.), 11 Apr. 1978.
Brent Michael
MacDonald Neal
Anamartic Limited
O'Connell Robert F.
Popek Joseph A.
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