Wafer scale burn-in testing

Details Wafer scale burn-in testing Wafer scale burn-in testing

1998-09-25

2000-09-19

Niebling, John F.

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

324765, G01R 3126, H01L 2166

Patent

active

06121065&

ABSTRACT:
A method of facilitating wafer level burn-in testing. The method may utilize a rerouting process to connect input and output connections of each chip on the wafer to a bus network. The bus network may be used to conduct wafer level burn-in testing and does not change the AC/DC operating characteristics of the chips.

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