Wafer sawing/grinding process

Details Wafer sawing/grinding process Wafer sawing/grinding process

1999-09-23

2001-07-24

Scherbel, David A. (Department: 3723)

Abrading

Abrading process

C451S041000, C451S054000, C029S412000, C029S413000, C029S414000, C029S415000, C029S417000

Reexamination Certificate

active

06264535

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88113715, filed Aug. 11, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a wafer sawing/grinding process. More particularly, the present invention relates to a wafer sawing/grinding process capable of removing cracks and chipping on the back surface of a silicon chip due to a wafer sawing operation.
2. Description of Related Art
Nowadays, most semiconductor devices are formed over a single-crystal silicon wafer. To increase production and lower production cost, the diameter of a silicon wafer has gradually increased from 4 inches in the past to 8 inches currently. Consequently, more silicon chips can be squeezed over a single wafer. However, due to limitations of the sawing operation and deformations preventions during pressure and thermal processing, an 8-inch silicon wafer must have a thickness at least between 700 to 800 micrometers.
In conventional semiconductor manufacturing process, a silicon wafer is first polished to form a mirror surface. The mirror surface of the silicon wafer then undergoes a series of operations including deposition, photolithographic operation, etching, doping and thermal processing to form devices and interconnections. In order to form a thin and lightweight package such as a thin small outline package (TSOP), the thickness of the silicon wafer must be further reduced. Therefore, before the silicon chips are sawn out for packaging, a tape is attached to the active surface of the wafer and the back surface is then ground until a thickness of about 100 to 300 micrometers. After the grinding operation, the tape is removed from the active surface. Another tape is attached to the back surface of the wafer and wafer sawing is carried out from the active surface to form a plurality of individual silicon chips. Since the area-to-thickness ratio increases tremendously after wafer grinding, transportation of the ground wafer and the process of removing tape from the active surface and the subsequent attachment of tape on the back surface of the wafer often produce cracks on the wafer.
Conventionally, wafer sawing is conducted after the thickness of the wafer has been reduced by grinding.
FIG. 1
is a schematic cross-sectional view of a sawn wafer produced by a conventional process. The cutting of silicon wafer is usually done by running the sawing blade from the active surface
12
of the wafer
10
along kerfs
18
between silicon chips
16
down towards the back surface
14
. Because thickness of the wafer has been reduced by grinding, stress created during the sawing operation often produces cracks
20
on the back surface
14
adjacent to the kerfs
18
.
FIG. 2
is a perspective view of one of the silicon chips in the wafer shown in FIG.
1
. Aside from cracks
20
, chipping
22
also contribute additional damages to the back surface
14
of the silicon chip
16
. In subsequent chip packaging operations such as a molding or encapsulation, and assembly operations such as surface mounting of the package, the silicon chip
16
is heated. Due to heating, the cracks
20
on the silicon chip
16
may extend. Ultimately, reliability of the product is compromised.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a wafer sawing/grinding process capable of preventing crack formation due to a sawing operation.
A second object of this invention is to provide a wafer sawing/grinding process capable of removing cracks and chipping that resulted from a sawing operation.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a wafer sawing/grinding process. First, a silicon wafer having an active surface and a back surface is provided. A first tape is attached to the back surface of a silicon wafer and then the wafer is sawn along the kerf between neighboring silicon chips. A second tape is attached to the active surface of the silicon wafer before removing the first tape. The back surface of the wafer is ground until the wafer reaches a desired thickness. Finally, a third tape is attached to the ground back surface of the wafer before removing the second tape.
Because the back surface is ground only after the wafer is sawn, any cracks or chipping formed during the sawing operation can be removed by grinding. Moreover, the wafer has a greater thickness when the wafer is sawn. Hence, cracking of the silicon chips is minimized.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5622900 (1997-04-01), Smith
patent: 5872046 (1999-02-01), Kaeriyama et al.
patent: 5964210 (1999-10-01), Hodsden

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