Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Reexamination Certificate
2008-07-16
2009-12-08
Quach, Tuan N. (Department: 2893)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
C438S465000, C257SE21599
Reexamination Certificate
active
07629230
ABSTRACT:
A wafer processing method for dividing, along streets, a wafer having a device area where devices are formed in a plurality of areas sectioned by the plurality of streets arranged in a lattice pattern on the front surface of a substrate and a peripheral extra area and comprising electrodes which are embedded in the substrate of the device area, comprising a dividing groove forming step for forming dividing grooves having a depth corresponding to the final thickness of each device along the streets; an annular groove forming step for forming an annular groove having a depth corresponding to the final thickness of each device along the boundary between the device area and the peripheral extra area; a protective member affixing step for affixing a protective member to the front surface of the wafer; a rear surface grinding step for grinding a rear surface corresponding to the device area of the substrate of the wafer to expose the dividing grooves and the annular groove to the rear surface of the substrate of the wafer and form an annular reinforcing portion in an area corresponding to the peripheral extra area; and a rear surface etching step for etching the rear surface of the substrate of the wafer to project the electrodes from the rear surface of the substrate.
REFERENCES:
patent: 7115485 (2006-10-01), Priewasser
patent: 7195988 (2007-03-01), Nemoto et al.
patent: 7559826 (2009-07-01), Sekiya
patent: 3537447 (2004-03-01), None
patent: 98/19337 (1998-05-01), None
Kajiyama Keiichi
Sekiya Kazuma
Disco Corporation
Quach Tuan N.
Smith , Gambrell & Russell, LLP
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