Wafer processing method

Details Wafer processing method Wafer processing method

2006-06-21

2009-12-01

Nguyen, Ha Tran T (Department: 2829)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Thinning of semiconductor substrate

C438S940000, C438S959000, C438S977000

Reexamination Certificate

active

07625810

ABSTRACT:
A method of processing a wafer having a device area where a plurality of devices are formed on the front surface and an extra area surrounding the device area and comprising electrodes which are formed in the device area, comprising: a reinforcement forming step for removing an area, which corresponds to the device area, in the back surface of the wafer to reduce the thickness of the device area to a predetermined value and keeping an area, which corresponds to the extra area, in the back surface of the wafer to form an annular reinforcement; and a via-hole forming step for forming a via-hole in the electrodes of the wafer which has been subjected to the reinforcement forming step.

REFERENCES:
patent: 6951811 (2005-10-01), Sorimachi
patent: 7135385 (2006-11-01), Patwardhan et al.
patent: 7244663 (2007-07-01), Kirby
patent: 2003-163323 (2003-06-01), None

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