Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-04-05
2005-04-05
Guerrero, Maria F. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S614000, C438S624000, C438S627000, C438S637000, C438S958000
Reexamination Certificate
active
06875681
ABSTRACT:
A wafer passivation structure and its method of fabrication is described. According to one embodiment of the present invention a metal layer having a bond pad spaced by a gap from a metal member is formed on a substrate. A first dielectric layer is then formed over the bond pad and the metal member and completely fills the gap. Next a second dielectric layer, having a dielectric constant greater than the first dielectric layer and being hermetic is formed over the first dielectric layer. In another embodiment of the present invention a first dielectric layer is formed on the top surface of a bond pad of a substrate. A second dielectric layer is then formed on the first dielectric. An opening is then formed through the first and second dielectric layers so as to expose the top surface of the bond pad. A barrier layer is then deposited on the sides of the opening and on the top surface of the bond pad. A contact is then formed on the barrier layer in the opening.
REFERENCES:
patent: 4921810 (1990-05-01), Kunieda et al.
patent: 4927505 (1990-05-01), Sharma et al.
patent: 5023205 (1991-06-01), Reche
patent: 5136364 (1992-08-01), Byrne
patent: 5260600 (1993-11-01), Harada
patent: 5354695 (1994-10-01), Leedy
patent: 5369299 (1994-11-01), Byrne
patent: 5559056 (1996-09-01), Weiler
patent: 5563102 (1996-10-01), Michael
patent: 5565384 (1996-10-01), Havemann
patent: 5587336 (1996-12-01), Wang et al.
patent: 5612254 (1997-03-01), Mu et al.
patent: 5661082 (1997-08-01), Hsu et al.
patent: 5677239 (1997-10-01), Isobe
patent: 5693565 (1997-12-01), Camilletti et al.
patent: 5698456 (1997-12-01), Bryant et al.
patent: 5759906 (1998-06-01), Lou
patent: 5767010 (1998-06-01), Mis et al.
patent: 5883001 (1999-03-01), Jin et al.
patent: 5900668 (1999-05-01), Wollesen
patent: 5989992 (1999-11-01), Yabu et al.
patent: 6025275 (2000-02-01), Efland et al.
patent: 6143638 (2000-11-01), Bohr
patent: 6204074 (2001-03-01), Bertolet et al.
Chen George
Guerrero Maria F.
Intel Corporation
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