Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-08-17
2002-04-30
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S106000, C324S765010, C324S754090, C324S755090, C324S760020
Reexamination Certificate
active
06379982
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to manufacturing, burning-in, testing, and mounting of semiconductor chips having integrated circuits. More particularly, the present invention relates to wafer-scale manufacturing, burning-in, testing, and mounting of semiconductor chip, or die, packages.
2. Background of the Invention
Typically, when manufacturing a dynamic random access memory device, for example, the manufacturing process includes constructing a semiconductor wafer of a preselected diameter which contains a plurality of individual dies. Currently, the diameter of a typically sized semiconductor wafer will frequently range from approximately 100 mm to approximately 300 mm, but wafers can be sized to have diameters which are smaller or larger than the typical diameterical range. The individual dies are singulated, or severed, from the wafer and are individually placed in packages, including but not limited to, small outline j-lead packages (SOJ), tape automated thin small outline packages (TSOP), chip scale packages (CSP), or any other of a wide variety of chip packages known within the art. After incorporating the individual dies in respective die, or chip, packages, the individual chip packages are often taken through a preburn-in test, a burn-in test which is usually conducted at elevated temperatures and voltages, and low and high speed final tests. Those chips which successfully complete each of the tests are ultimately installed upon the next higher assembly such as a circuit board, flexible substrate, or some other structure to provide a memory device, for example, and which will ultimately be incorporated in an electronic component, or product.
However, with a constant demand on the semiconductor chip industry for providing an ever increasing number of transistors on a single semiconductor chip, to increase memory capacity and/or speed for example, the industry must continuously find ways to overcome problems and inefficiencies encountered in the manufacturing, burning-in, testing, and mounting of chips on the next higher level of assembly so as to remain competitive in the market place. To illustrate, more and more transistors, or devices, are being provided within a given semiconductor die, or chip, and are becoming by necessity larger in size to accommodate the increasing number of transistors, which can range upward of a hundred million (100×10
6
) individual transistors on a single chip. Thus, it is desirable, if not required, that the final chip package be made as small as possible to counter the physically larger dies contained therein.
One of the technical problems encountered by the industry in such ultra large scale integration (ULSI) technology is how to control, and preferably reduce, the costs associated with burning-in, testing, and then mounting dies on the next higher assembly such as on circuit boards or various substrates to be used in a given end product.
Another problem encountered in manufacturing larger sized dies designed to accommodate an ever increasing number of transistors, or devices, is contending with the stray inductance and parasitic capacitance associated with bondwires extending between the input and output bond pads located on the active surface of the die and bond pads or lead frames of the package that are in turn placed in electrical communication with various circuits on the next level of assembly. For example, a typical bond pad, or contact pad, may have a self-inductance of approximately 3-10 nanohenries (nH) and a typical bond pad, or contact pad, may have a stray capacitance of 0.2 picofarads (pF). Such unwanted, relatively large self-inductances and stray capacitances can become very troublesome upon chip frequencies approaching and exceeding 1 gigahertz.
A further problem encountered when manufacturing chips accommodating a large number of transistors is being able to quickly and reliably test and burn the chips at either a wafer level, or at a packaged chip level, without damaging the bond pads located on the active surface of the chip, or in the alternative, without damaging an electrical lead or an electrical contact that is accessible from the exterior of the chip package.
Other manufacturing and testing difficulties arise from the need to constantly update expensive test equipment as each new generation of chip packages are designed and introduced to the market. This is because such test equipment will often utilize elongated probes or cantilevered probes that resiliently extend from a structure referred to as a probe head, or probe card, in a preselected pattern to make electrical contact with a respective die bond pad either directly, or by temporarily contacting an externally accessible lead, pin, or contact if the die has already been packaged, so that burn-in and testing can be conducted.
A wafer level burn-in system is disclosed in U.S. Pat. No. 5,866,535 issued to Budnaitis which includes a semiconductor wafer being placed in a burn-in apparatus so that bond pads on the active surface of the wafer faces upwardly. The system further includes a laminated contact sheet which is positioned on top of the active surface of the wafer and a temporary, compliant, selectively conductive Z-axis member which is positioned on top of the laminated contact sheet, and a movable base unit is positioned above the stacked components of the system. The base unit is then biased downward to electrically couple the base unit, the Z-axis member, the laminated contact sheet, and the bond pads of the wafer so that burn-in and testing of the wafer can be conducted. Upon burning-in and testing of the wafer, the wafer, as well as the various components, are removed from the test apparatus and disassociated from each other so that the wafer can be forwarded for further processing.
U.S. Pat. No. 6,005,401 issued to Nakata et al. discloses a semiconductor wafer burn-in and test apparatus including a retainer board for holding a semiconductor wafer which in turn is brought into contact with a probe sheet having probe terminals corresponding to terminals on the semiconductor wafer so that burn-in and testing can be conducted on the chips or integrated circuits present on the wafer. An elastic member compensates for any unevenness that may exist with respect to the probe terminals of the probe sheet upon contacting the wafer with the probe sheet.
U.S. Pat. No. 5,959,462 issued to Lum discloses a test structure for burn-in testing of a semiconductor wafer in which the test structure incorporates a backing support wafer in which a plurality of segmented individual test integrated circuits have been attached to the backing support wafer. Conductive bumps of the attached integrated circuits which are attached to the support wafer are brought into electrical contact with integrated circuits on the product wafer so that burn-in testing can be conducted. After burn-in and testing of the product wafer, the test structure, incorporating the backing support wafer and the attached integrated circuits, is removed from electrical contact with the product wafer and the product wafer is then forwarded for further processing. The test structure of Lum is quite elaborate in that yet another silicon wafer mold upon which a thin film signal distribution layer containing various electrical signal routing circuits, optional electrical interconnects and contacts as needed between the layers of thin film signal distribution layer is used in the construction of the test structure for stabilizing the test integrated circuits as they are being attached to the backing support wafer.
U.S. Pat. No. 6,004,867 issued to Kim et al. discloses a chip package assembled at the wafer level which incorporates a silicon substrate attached to the active surface of the wafer which contains a plurality of input/output pads thereon. The substrate includes a top surface and a bottom surface. The bottom surface of the substrate is provided with a plurality of circuit traces configured to terminate at preselected positions o
Ahn Kie Y.
Forbes Leonard
Luk Olivia
Micro)n Technology, Inc.
Niebling John F.
TraskBritt
LandOfFree
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