Wafer of semiconductor material for fabricating integrated devic

Details Wafer of semiconductor material for fabricating integrated devic Wafer of semiconductor material for fabricating integrated devic

1995-12-13

1999-01-05

Dang, Trung

Metal treatment

Barrier layer stock material, p-n type

With non-semiconductive coating thereon

438455, 438406, H01L 25265

Patent

active

058556931

ABSTRACT:
A wafer of semiconductor material for fabricating integrated devices, including a stack of superimposed layers including first and second monocrystalline silicon layers separated by an intermediate insulating layer made of a material selected from the group comprising silicon carbide, silicon nitride and ceramic materials. An oxide bond layer is provided between the intermediate layer and the second silicon layer. The wafer is fabricated by forming the intermediate insulating layer on the first silicon layer in a heated vacuum chamber; depositing the oxide layer; and superimposing the second silicon layer. When the stack of silicon, insulating material, oxide and silicon layers is heat treated, the oxide reacts so as to bond the insulating layer to the second silicon layer. As a ceramic material beryllium oxide, aluminium nitride, boron nitride and alumina may be used.

REFERENCES:
patent: 5413952 (1995-05-01), Pages et al.
Horiuchi et al.; "Reduction of P-N Junction Leakage Current by Using Poly-si Interlayered SOI Wafers"; IEEE Transactions on Electron Devices, vol. 42, No. 5, May 1995, pp. 876-882.
Partial European Search Report from European Patent Application 94830577.6, filed Dec. 15, 1994.
Research Disclosure, No. 345, Jan. 1993 Havant GB, p. 76 "Wafer-Bonding With Diamond-Like Carbon Films".
Patent Abstracts of Japan, vol. 11, No. 88 (E-490), Mar. 18, 1987 & JP-A-61 240629 (NEC Corp.).

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