Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2006-06-13
2006-06-13
Chang, Rick K. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S846000, C029S830000, C029S843000, C029S739000, C029S740000, C029S840000, C174S050510, C361S760000, C439S066000, C439S068000, C439S072000, C439S074000, C439S075000
Reexamination Certificate
active
07059048
ABSTRACT:
A method for connecting electronic components, such as, an integrated circuit die and a package substrate, is described. According to one aspect of the invention, a contact pad protective material is applied on one or more of the contact pads on an integrated circuit die. The underfill material is applied to the surface of the die not covered by the contact pad protective material and the underfill material is partially cured in a curing oven. The contact pad material is removed leaving openings over the respective surface of the contact pad. A one or more contacts on a package substrate is inserted into the openings, electronically connecting the contacts to the contact pads.
REFERENCES:
patent: 3915729 (1975-10-01), Eustice
patent: 3998374 (1976-12-01), Cranston et al.
patent: 6756540 (2004-06-01), Hedler et al.
Burress, Robert V., Capote, Albert M., Lee, Yong-Joon, Lenos, Howard A., & Zamora, Jeffrey F. “A Practical, Flip-Chip, Multi-layer Pre-Encapsulation Technology for Wafer-Scale Underfill” 2001 Electronic Components and Technology Conference 2001 IEEE.
Gilleo, Dr. Ken & Blumel, David. “Transforming Flip Chip into CSP with Reworkable Wafer-Level Underfill” Alpha Metals Jersey City, NJ, pp. 159-165 1999.
Johnson, Dustin C., Baldwin Ph.D., Daniel F. “Wafer Scale Packaging Based on Underfill Applied at the Wafer Level for Low-Cost Flip Chip Processing” 1999 Electronic Components and Technology Conference. 1999 IEEE.
Nguyen L., and Nguyen, H. “Solder Joint Shape Formation Under Constrained boundaries in Wafer Level Underfill” 2000 Electronic Components and Technology Conference. 2000 IEEE.
Crane Ph.D., Lawrence, Torres, Ph.D., Alfranio & Yaeger, Erin. “Reworkable Underfills Development, Processing and Reliability” Laboratory for Advance Electronic Packaging Auburn University. Sep. 1, 1998.
Ma, Bodan; Tong, Quinn K.; Zhang Eric, Hong, Sun Hae & Savoca, Ann “Materials Challenges for Wafer-Level Flip Chip Packaging” 2000 Electronic Components and Technology Conference, 2000 IEEE.
Tong, Quinn K.; Ma, E.; Zhang Eric, Hong, Savoca, Ann; Nguyen, L.; Quentin, C.; Luo, Shijian H.; Li, Fan L. & Wong, C.P. “Recent Advances on a Wafer-Level Flip Chip Packaging Process” 2000 Electronic Components and Technology Conference. 2000 IEEE.
Keser, Beth; Yeung, Betty; White, Jerry, & Fang Treliant. “Encapsulated Double-Bump WL-CSP: Design and Reliability” 2001 Electronic Components and Technology Conference. 2001 IEEE.
Shi, S.H.; Yamashita, T.; and Wong, C.P. “Development of the Wafer Level Compressive-Flow Underfill Process and Its Required Materials” 1999 Electronic Components and Technology Conference. 1999 IEEE.
Nguyen, L.; Kelkar, N.; and Takiar H. “A Manufacturing Perspective of Wafer Level CSP” 2000 Electronic Components and Technology Conference. 2000 IEEE.
Topper, M.; Auersperg J.; Glaw, V.; Kaskoun, K.; Prack E. Keser, B.; Coskina, P.; Jager, D.; Ehrmann, Petter O.; Samulewicz, K.; Meinherz, C.; Fehlberg, S.; Karduck, C.; Reichl, H. “Fab Integrated Packaging (FIP) A New Concept for High Reliability Wafer-Level Chip size Packaging” 2000 Electronic Components and Technology Conference. 2000 IEEE.
Lau, John H. “Critical Issues of Wafer Level Chip Scale Package (WLCSP) With Emphasis On Cost Analysis and Solder Joint Reliability” 2000 IEEE/CPMT Int'l Manufacturing Technology Symposium. 2000 IEEE.
Crane, Larry; Konarski, Mark, Yaeger, Erin “Compatibility of Current Flipchip Process with Lead Free Solder Bumps” International Microelectronics and Packaging Society Nordic Chapter. Sep. 23-26, 2001.
Koning Paul
Sterrett Terry
Blakely , Sokoloff, Taylor & Zafman LLP
Chang Rick K.
Intel Corporation
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