Wafer level underfill and interconnect process

Details Wafer level underfill and interconnect process Wafer level underfill and interconnect process

2005-11-22

2005-11-22

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

C257S788000, C257S789000, C257S793000, C257S795000

Reexamination Certificate

active

06967412

ABSTRACT:
A chip scale package and a method for its manufacture which include providing sticky interconnects on a surface of a semiconductor die, the interconnects being surrounded by a layer of thermal epoxy.

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MOSFET BGA Design Guide 2004-Fairchild Semiconductor, pp. i-ii and pp. 1-43.

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