Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2000-06-16
2002-04-30
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S723000, C257S773000, C257S774000, C257S786000, C361S760000, C438S108000, C438S109000
Reexamination Certificate
active
06380629
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a stack package and a method of fabricating the same, more particularly to a stack package consisting of at least two stacked semiconductor chips and a method of fabricating the same.
2. Description of the Related Art
Rapid progress in the memory chip has been presented to increase memory capacity. Currently, 128 M DRAM is mass-produced, and also the mass-production of 256 M DRAM will be available sooner or later.
To increase memory chip capacity, i.e. the high integration, a technology for inserting cells as many as possible into a given area of semiconductor device, is widely known. However, this method requires high technology such as a precise line width and a considerable amount of time for development. Accordingly, a relatively simpler stacking technology to optimize integrity of the semiconductor device has been developed most recently.
The term “stacking” used in semiconductor industry means a technique to double the memory capacity by heaping up at least two semiconductor chips in a vertical direction. According to the stacking technique, a 128 M DRAM device can be constituted by two 64 M DRAM devices for instance, also a 256 M DRAM device can be constituted by two 128 M DRAM devices.
Merely an example of a package fabricated according to the typical stacking technique is illustrated in
FIGS. 1 and 2
.
As shown in
FIG. 1
, a lead frame
2
is attached by means of an adhesive to a semiconductor chip
1
in which a bond pad is disposed on an upper portion thereof. An inner lead
21
of the lead frame
2
is connected to the bondpad with a metal wire
3
. The entire resultant is sealed with a molding compound
4
such that both ends of an outer lead
22
of the lead frame
2
are protruded therefrom.
On the package as constituted above, another package having the same constitution as above is stacked. That is to say, the outer lead
22
of the package in the upper position is in contact with a midway portion of the lead frame
2
in the lower position thereby electrically connecting each other.
However, there is a drawback in the general stack package that the whole thickness of the package is too thick. Furthermore, since an electrical signal should pass the lead frame of the lower package through the outer lead of the upper package, there is another drawback that the electrical signal path is too long. Especially, bad connections are frequently occurred due to bad soldering since leads of both upper and lower packages are joined with each other by soldering.
A conventional stack package to solve foregoing problems is illustrated in FIG.
2
.
As shown in the drawing, upper and lower semiconductor chips
1
a
and
1
b
are attached each other. An inner lead
21
a
of an upper lead frame
2
a
is attached on the upper surface of the upper semiconductor chip
1
a.
The inner lead
21
a
of the upper semiconductor chip
1
a
is electrically connected to a bonding pad of the upper semiconductor chip
1
a
with a metal wire (not shown) . Further, an inner lead
21
b
of a lower lead frame
2
b
is attached on the bottom surface of the lower semiconductor chip
1
b.
The inner lead
21
b
of the lower lead frame
2
b
is electrically connected to a bonding pad of the lower semiconductor chip
1
b
with a metal wire(not shown).
An outer lead
22
a
of the upper lead frame
1
a
is electrically bonded at a midway portion of the lower lead frame by the laser and an outer lead
22
b
of the lower lead frame
2
b
is protruded from a molding compound
5
.
However, it is impossible to manufacture the wafer level stack package since stacking and packaging steps for each semiconductor chip should be performed in the foregoing conventional stack package.
Furthermore, the lead frame electrically connecting each semiconductor chip and transmitting electrical signals outside is too long to conduct. Although a pattern tape instead the lead frame is used, the results will be the same.
SUMMARY OF THE INVENTION
Accordingly, the present invention is provided to solve the foregoing problems of the conventional devices and it is one object to provide a wafer level stack package constituted by stacking at least two semiconductor chips in the wafer level and a method of fabricating the same.
Another object of the present invention is to improve electrical conductivity performance by shortening the electrical signal transmission path.
To accomplish the above objects, the wafer level stack package according to the present invention consists as follows.
Bond pads are formed on each first face of upper and lower semiconductor chips, and the upper and the lower semiconductor chips are arranged such that their first faces are opposed to each other with a selected distance. First insulating layers is coated on the respective first faces of the semiconductor chips so that their bond pads are exposed the first insulating layer. Upper and lower metal patterns whose one ends are connected to the respective bond pads and the other ends are extended toward the contours of the respective semiconductor chips. Meanwhile, on the upper semiconductor chip, a through hole exposing the respective other ends of the upper and the lower metal patterns is formed along the contour of the semiconductor chip. Second insulating layers are coated on the respective first insulating layers of the semiconductor chips and the second insulating layers are adhered to each other thereby forming one body of the upper and the lower semiconductor chips as a stack structure. There is deposited a medium pattern for electrically connecting the respective other ends of the upper and the lower metal patterns at an inside wall of the through hole.
A pattern film is adhered on a second face of the upper semiconductor chip opposite to the first face of the upper semiconductor chip. The pattern film comprises an insulating film and a metal line arranged inside the insulating film. One end of the metal line is exposed from the insulating film thereby forming a ball land. And, the other end of the metal line is exposed through both sides of the insulating film. A metal wire is extended from the other end of the metal line through the through hole, and the metal wire is bonded on the medium pattern. The through hole is filled with a molding compound whose top surface is in the same plane as that of the pattern film. Solder balls are mounted at the ball land of the pattern film.
A method of fabricating the wafer level stack package as constructed above is as follows.
First insulating layers are coated on each first face of two wafers constituted a plurality of semiconductor chips therein, and then the first insulating layers are etched thereby exposing bond pads of the respective semiconductor chips. A metal layer is deposited on the first insulating layers respectively, then patterned thereby forming a metal pattern whose one end is connected to the bond pads and the other end is extended toward the contours of the respective semiconductor chips. Second insulating layers are coated on the respective first insulating layers and then the second insulating layer of a selected wafer is etched thereby exposing the other end of the metal pattern in the selected wafer.
Afterward, the second insulating layers are confronted and adhered to each other so that two wafers are overlapped. At this time, the wafer whose the other end of the metal pattern is exposed from the second insulating layer is disposed at a lower portion. Since a through hole is formed by partially removing the contours of the semiconductor chips formed on the upper wafer, the respective other ends of the upper and the lower metal patterns are exposed via the through holes. A medium pattern is deposited on an inside wall of the through holes, thereby electrically connecting the other ends of an upper metal pattern of the upper wafer and a lower metal pattern of the lower wafer.
Meanwhile, a pattern film having an arrangement of metal lines in the insulating film is provided. One end of the metal line is expo
Chu Chris C.
Hyundai Electronics Industries Co,. Ltd.
Lee Eddie
Pillsbury & Winthrop LLP
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