Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-01-25
2005-01-25
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S618000, C438S666000, C438S671000, C438S197000, C438S585000
Reexamination Certificate
active
06846740
ABSTRACT:
Methods in accordance with the present invention provide a quasi-planarized surface between one or more semiconductor devices and at least a portion of surrounding passivation material, where the devices have different elevations above a substrate. A hard mask defines the planarized surface as the interface between the hard mask and both the passivation layer and the device, after a passivation layer etching process. The resulting planarized surface has a small to zero step height, is insensitive to passivation layer non-uniformity and etch non-uniformity, provides full passivation of the device side wall, provides protection for the device against etch-induced damage, and prevents the detrimental effects of passivation layer voids. The methods are applicable to semiconductor device fabrication for electronic and photonic/optoelectronic systems such as, but not limited to, cell phones, networking systems, high brightness (HB) LEDs, laser diodes (LDs), photodiodes, modulator diodes and multifunction solar cells.
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Demir Hilmi Volkan
Fidaner Onur
Miller David Andrew Barclay
Sabnis Vijit
Zheng Jun-Fei
Luu Choung Anh
Schwabe Williamson & Wyatt P.C.
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