Wafer level packaging cap and fabrication method thereof

Details Wafer level packaging cap and fabrication method thereof Wafer level packaging cap and fabrication method thereof

2006-01-26

2009-08-25

Vu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

C257S773000, C257S774000, C257SE23182

Reexamination Certificate

active

07579685

ABSTRACT:
A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.

REFERENCES:
patent: 2004/0077154 (2004-04-01), Nagarajan et al.
patent: 2004/0259325 (2004-12-01), Gan
patent: 2005/0073040 (2005-04-01), Lee et al.
patent: 2007/0004079 (2007-01-01), Geefay et al.
patent: 1071126 (2001-01-01), None
patent: 1199744 (2002-04-01), None

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