Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-03-12
2004-07-13
Williams, Alexander Oscar (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S620000, C257S784000, C257S786000, C257S698000, C257S211000, C257S208000, C257S203000, C257S207000, C324S765010, C324S073100, C324S537000, C324S1540PB
Reexamination Certificate
active
06762431
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a wafer-level package, a method of manufacturing thereof, and a method of manufacturing semiconductor devices from such a wafer-level package. The present invention particularly relates to an improved wafer-level package to be tested by a preliminary test (PT) and a final test (FT), a method of manufacturing the wafer-level package, and a method of manufacturing semiconductor devices using such a wafer-level package.
Recently, there is a need for more efficient manufacturing and testing processes of semiconductor devices. In order to achieve this, a full test (including PT and FT) is implemented on an uncut semiconductor wafer before being cut into individual semiconductor devices. As will be described below, the full test has several advantages over the related art in which the semiconductor wafer is cut into individual semiconductor devices and each of the semiconductor devices are tested individually.
The advantages include good handling efficiency, a possibility of sharing certain equipment and reduced space. If the wafer sizes are equal, handling equipment can be shared. Also, it is possible to save space otherwise taken up as a storage area and/or an installation area when accommodating individualized semiconductor devices (LSI chips) in containers such as a tray.
For higher density mounting, there is an increasing need for a KGD (Known-Good Die) and a real-chip-size package (a package having the same size as that of the semiconductor chip). However, with the package structure of the semiconductor device of the related art, which does not correspond to the KGD or the real-chip-size package, the area of the package is greater than that of the semiconductor chip. Therefore, the semiconductor wafer must be individualized at some point before packaging. Thus, with the package structure of the related art, the entire process, that is to say, from a manufacture process to a test process, cannot be implemented on the semiconductor wafer.
However, with the KGD or the real-chip-size package, since the final package configuration corresponds to the area of the semiconductor chip, the entire process can be implemented on the semiconductor wafer. Therefore, the above-described advantages can be obtained.
2. Description of the Related Art
Recently, there is an increasing interest in a wafer-level package which is a package structure with which the entire process from the manufacturing process to the testing process can be implemented on a semiconductor wafer. The wafer-level package includes a semiconductor wafer provided with a plurality of semiconductor chip circuits with chip terminals, external connection terminals, redistribution traces connecting the chip terminals and the external connection terminals, and an insulating material such as a sealing resin. The insulating material is provided for protecting the semiconductor chip circuits and the redistribution traces. A structure without the insulating material is also possible.
The wafer-level package may be used in two different configurations. One is in the form of a wafer (i.e., before being cut) and the other is in form of individual semiconductor devices (i.e., after cutting into individual semiconductor chip circuits.)
In the following, the wafer-level package of the above-described structure will be described with regard to a test process thereof. With the wafer-level package, like that of the semiconductor devices of other configurations, the manufacture process includes a test process. The test process generally includes a preliminary test (PT) and a final test (FT).
The PT is a test implemented before providing the insulating material. The PT is a general test such as a conduction test of the interconnections, and thus does not include the operation test of the semiconductor chip circuit itself. Since the PT is implemented before providing the insulating material, the PT can be implemented using the chip terminals provided on the semiconductor chip circuit.
The PT is particularly advantageous for the package structure of the semiconductor devices of the related art (hereinafter, referred to as a conventional package), which are not designed for the KGD or for the real-chip-size package. In a manufacture process of the conventional package, the PT is followed by a cutting process (i.e., dicing process) for individualizing the semiconductor wafer into the semiconductor devices. Then, only those semiconductor devices, which were determined good in the PT, are provided with the insulating material and undergo the FT. In other words, those semiconductor devices, which were determined bad in the PT, are not provided with the insulating material and also do not undergo the FT. Thus, the manufacture efficiency can be improved.
The FT is implemented after providing the insulating material. The FT is a total test including the operation test of the semiconductor chip circuit. Since the FT is implemented after the insulating material has been provided, the FT can only be implemented using the external connection terminals exposed from the insulating material. In other words, the terminals (such as the chip terminals) other than those generally used by the users are not exposed. Therefore, the chip terminals sealed in the insulating material cannot be used in the FT.
Therefore, in the related art, the wafer level package is tested by, first, implementing the PT before providing the insulating material using the chip terminals which are not yet covered with the insulating material. After the PT, the insulating material is provided, and then the FT is implemented using the external connection terminals exposed from the insulating material.
In the test process of the related art, the object of implementing the PT is to improve manufacture efficiency by avoiding the insulating material being provided on bad semiconductor devices and thus avoiding the FT being implemented thereon. On the contrary, with the wafer-level package, all semiconductor chip circuits, including circuits of the bad semiconductor devices, are provided with the insulating material and undergo the FT, so that it is not necessary to implement the PT before the FT.
Also, as has been described above, the wafer-level package is used for simplifying the manufacture process by using the semiconductor wafer from the manufacture process to the test process. For further simplifying the manufacture process, the PT and the FT, which in the related art were implemented as two separate tests, can be integrated into a single test process.
When the PT and the FT are integrated into a single test process, the integrated test process can be carried out either before providing the insulating material (i.e., when the PT is implemented in the related art) or after providing the insulating material (i.e., when the FT is implemented in the related art). When the integrated test process is implemented before providing the insulating material, it is not possible to detect any failure produced in the semiconductor chip circuit while providing the insulating material. Thus, the test process should be implemented in a later step in the manufacture process of the semiconductor device.
On the contrary, when the integrated test process is implemented after providing the insulating material, only the external connection terminals exposed from the insulating material may be connected to test equipment (e.g., a semiconductor tester). That is to say, the chip terminals include terminals which do not serve as the external connection terminals, but can be used for testing the semiconductor chip circuit (hereinafter referred to as test chip terminals). There is a drawback that the test chip terminals will be covered with the insulating material, so that the test using the test chip terminals cannot be implemented after providing the insulating material.
In order to avoid such a drawback, test terminals may be provided in a region of the semiconductor chip circuit region, which terminals are exposed from t
Westerman Hattori Daniels & Adrian LLP
Williams Alexander Oscar
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