Wafer level package with air pads and manufacturing method...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Solder wettable contact – lead – or bond

Reexamination Certificate

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C257S780000

Reexamination Certificate

active

07141885

ABSTRACT:
A structure for improving electrical performance and interconnection reliability of an integrated circuit in a Wafer Level Packaging (WLP) application comprises an air pad located under an interconnection metal solder pad. Using a low dielectric material such as air underlying the interconnection pad, pad capacitance is reduced, thereby improving the speed of associated electrical signal transitions. By configuring the structure to have interconnection pad supports at only a limited number of pad periphery points, a cured soldered connection can absorb mechanical stresses associated with divergent movement between a connecting wire and the interconnection pad. Such a structure can be manufactured using the steps of: 1) depositing a soluble base material in a cavity on an IC substrate, 2) depositing a metal pad layer on the soluble base layer, and 3) dissolving the soluble base layer, leaving an air gap under the metal pad layer which is supported by the periphery supports.

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patent: 6333565 (2001-12-01), Hashimoto
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patent: 0 529 503 (1993-03-01), None
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patent: 2000133920 (2000-05-01), None
Kohl, Paul A.; Martin, Kevin, “Wafer-Level Packaging Addresses Chip-to-Module Interconnections” Semiconductor International, CAHNERS Business Information, Reed Elsevier, Inc. (Apr. 2001).
Kohl, Paul A., et al, “Air-Gaps for Electrical Interconnections”: Electrochemical and Solid-State Letters, 1(1):49-51, The Electrochemical Society, Inc. (1998).

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