Wafer level package incorporating dual stress buffer layers...

Details Wafer level package incorporating dual stress buffer layers... Wafer level package incorporating dual stress buffer layers...

2001-01-16

2002-08-13

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S778000

Reexamination Certificate

active

06433427

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a wafer level package having a multiplicity of IC dies formed thereon and a method for fabrication and more particularly, relates to a wafer level package having a multiplicity of IC dies thereon each incorporating dual stress buffer layers for I/O redistribution and a method for such fabrication.
BACKGROUND OF THE INVENTION
In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques in such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become more difficult.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C
4
) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C
4
technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C
4
technique. Similarly, the thin film electrodeposition technique which also requires a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C
4
technique. For instance, a conventional thin film electrodeposition process for depositing solder bumps is shown in FIGS.
1
A~
1
F.
A conventional semiconductor structure
10
is shown in FIG.
1
A. The semiconductor structure
10
is built on a silicon substrate
12
with active devices built therein. A bond pad
14
is formed on a top surface
16
of the substrate
12
for making electrical connections to the outside circuits. The bond pad
14
is normally formed of a conductive metal such as aluminum. The bond pad
14
is passivated by a final passivation layer
20
with a window
22
opened by a photolithography process to allow electrical connection to be made to the bond pad
14
. The passivation layer
20
may be formed of any one of various insulating materials such as oxide, nitride or organic materials. The passivation layer
20
is applied on top of the semiconductor device
10
to provide both planarization and physical protection of the circuits formed on the device
10
.
Onto the top surface
24
of the passivation layer
20
and the exposed top surface
18
of the bond pad
14
, is then deposited an under-bump metallurgy layer
26
. This is shown in FIG.
1
B. The under bump metallurgy (UBM) layer
26
normally consists of an adhesion/diffusion barrier layer
30
and a wetting layer
28
. The adhesion/diffusion barrier layer
30
may be formed of Ti, TiN or other metal such as Cr. The wetting layer
28
is normally formed of a Cu layer or a Ni layer. The UBM layer
26
improves bonding between a solder ball to be formed and the top surface
18
of the bond pad
14
.
In the next step of the process, as shown in
FIG. 1C
, a photoresist layer
34
is deposited on top of the UBM layer
26
and then patterned to define a window opening
38
for the solder ball to be subsequently formed. In the following electrodeposition process, a solder ball
40
is electrodeposited into the window opening
38
forming a structure protruded from the top surface
42
of the photoresist layer
34
. The use of the photoresist layer
34
must be carefully controlled such that its thickness is in the range between about 30 &mgr;m and about 40 &mgr;m, preferably at a thickness of about 35 &mgr;m. The reason for the tight control on the thickness of the photoresist layer
34
is that, for achieving a fine-pitched solder bump formation, a photoresist layer of a reasonably small thickness must be used such that a high imaging resolution can be achieved. It is known that, during a photolithography process, the thicker the photoresist layer, the poorer is the imaging process. To maintain a reasonable accuracy in the imaging process on the photoresist layer
34
, a reasonably thin photoresist layer
34
must be used which results in a mushroom configuration of the solder bump
40
deposited therein. The mushroom configuration of the solder bump
40
contributes greatly to the inability of a conventional process in producing fine-pitched solder bumps.
Referring now to
FIG. 1E
, wherein the conventional semiconductor structure
10
is shown with the photoresist layer
34
removed in a wet stripping process. The mushroom-shaped solder bump
40
remains while the under bump metallurgy layer
26
is also intact. In the next step of the process, as shown in
FIG. 1F
, the UBM layer
26
is etched away by using the solder bump
40
as a mask in an wet etching process. The solder bump
40
is then heated in a reflow process to form solder ball
42
. The reflow process is conducted at a temperature that is at least the reflow temperature of the solder material.
In recent years, chip scale packages (CSP) have been developed as a new low cost packaging technique for high volume production of IC chips. One of such chip scale packaging techniques has been developed by the Tessera Company for making a so-called micro-BGA package. The micro-BGA package can be utilized in an environment where several of the packages are arranged in close proximity on a circuit board or a substrate much like the arrangement of individual tiles. Major benefits achieved by a micro-BGA package are the combined advantages of a flip chip assembly and a surface mount package. The chip scale packages can be formed in a physical size comparable to that of an IC chip even though, unlike a conventional IC chip such as a flip chip, the chip scale package does not require a special bonding process for forming solder balls. Furthermore, a chip scale package may provide larger number of input/output terminals than that possible from a conventional quad flat package, even though a typical quad flat package is better protected mechanically from the environment.
In a typical micro-BGA package, a flexible interposer layer (which may contain circuit) is used to interconnect bond pads on an IC chip to an array of solder bump connections located on a flexible circuit. The flexible circuit, normally of a thickness of approximately 25 nm, is formed of a polymeric material such as polyimide which is laminated to a silicon elastomer layer of approximately 150 nm thick. The silicon elastomeric layer provides flexibility and compliance in all three directions for relief of stresses and thermal expansion mismatches. To further reduce the fabrication cost of IC devices, it is desirable that if a whole wafer can be passivated to seal the IC dies on the wafer, and then be severed into individual IC dies from the wafer such that not only the benefits of a chip scale package can be realized, the packaging cost for the IC dies may further be reduced.
The conventional flip-chip bonding process requires multiple preparation steps for IC chips, i.e.

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