Wafer level package incorporating dual compliant layers and...

Details Wafer level package incorporating dual compliant layers and... Wafer level package incorporating dual compliant layers and...

2005-07-05

2005-07-05

Lebentritt, Michael S. (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S778000, C257SE23021, C257SE23069, C257SE21508

Reexamination Certificate

active

06914333

ABSTRACT:
A wafer level package that incorporates dual compliant layers and a metal cap layer on top of I/O pads and a method for forming the package. The wafer level package includes a plurality of metal cap layers formed on top of a plurality of I/O pads to function as stress buffering and avoiding sharp corners in metal traces formed on top of the metal cap layers. A first compliant layer and a second compliant layer are formed under the metal trace to provide the necessary standoff and to accommodate differences in coefficients of thermal expansion of the various materials on an IC die. The wafer level package is particularly suitable for copper devices or in devices wherein copper lines are used.

REFERENCES:
patent: 5851911 (1998-12-01), Farnworth
patent: 6071755 (2000-06-01), Baba et al.
patent: 6235552 (2001-05-01), Kwon et al.
patent: 6277669 (2001-08-01), Kung et al.
patent: 6433427 (2002-08-01), Wu et al.
patent: 6743660 (2004-06-01), Lee et al.

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