Wafer-level package having test terminal

Details Wafer-level package having test terminal Wafer-level package having test terminal

2008-07-15

2008-07-15

Williams, Alexander O (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257SE23179, C257S786000, C257S620000, C257S203000, C257S207000, C257S211000, C257S698000, C257S696000, C324S537000, C324S073100, C324S765010

Reexamination Certificate

active

11433396

ABSTRACT:
A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.

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Office Action dated Jan. 30, 2007, issued in corresponding Japanese Application No.: 10-374804.

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