Wafer level package and method of fabricating the same

Details Wafer level package and method of fabricating the same Wafer level package and method of fabricating the same

2011-07-26

2011-07-26

Cao, Phat X (Department: 2813)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S779000, C257SE21521

Reexamination Certificate

active

07985697

ABSTRACT:
Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate. Therefore, in comparison with a conventional wafer level package fabricated using the via process, it is possible to simplify a fabrication process and reduce production cost.

REFERENCES:
patent: 6743656 (2004-06-01), Orcutt et al.
patent: 2004/0077154 (2004-04-01), Nagarajan et al.
patent: 2006/0152615 (2006-07-01), Kwon et al.
patent: 2007-189032 (2007-07-01), None
patent: 10-2006-0081201 (2006-07-01), None
“Characterization and Reliability Verification of Wafer-Level Hermetic Package with Nano-Liter Cavity for RF-MEMS Applications ”, Suk-Jin Ham et al., pp. 1127-1134, 2007 Electronic Components and Technology Conference.

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