Wafer level package and method for making the same

Details Wafer level package and method for making the same Wafer level package and method for making the same

2005-12-22

2009-02-17

Garber, Charles D. (Department: 2812)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Physical stress responsive

Reexamination Certificate

active

07491568

ABSTRACT:
The present invention relates to a wafer level package and method for making the same. The method of the invention comprises: (a) providing a metal layer, the metal layer having a first surface and a second surface; (b) forming a plurality of first caves and a plurality of second caves on the first surface; (c) forming a cover in each first cave and around each first cave and forming a conductive portion in each second cave and around each second cave; (d) disposing a wafer onto the covers and the conductive portions; and (e) removing the metal layer. Whereby the process of the invention will be shortened and the cost will decrease. The method of invention provides the conductive portions used for convenient leads connecting with outer components and further decreases the size of the package.

REFERENCES:
patent: 6392144 (2002-05-01), Filter et al.
patent: 6492203 (2002-12-01), Wakashima et al.
patent: 6562656 (2003-05-01), Ho
patent: 6724705 (2004-04-01), Lee et al.

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