Wafer level integration and testing

Details Wafer level integration and testing Wafer level integration and testing

1992-10-16

1994-11-22

Thomas, Tom

Fishing, trapping, and vermin destroying

437 51, H01L 2166, G01R 3126

Patent

active

053669061

ABSTRACT:
In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.

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"Bare Chip Test Techniques for Multichip Modules" by R. A. Fillion, et al, GE Corporate Research and Development Center, Schenectady, N.Y.
"Status and Update on the GE HDI Multichip Module Technology" by R. A. Fillion, et al, GE Corporate Research and Development Center, Schenectady, N.Y.

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