Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2003-03-11
2004-05-04
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S783000, C257S738000
Reexamination Certificate
active
06731003
ABSTRACT:
BACKGROUND OF THE INVENTION
There are a number of ways to form conductive bumps on a semiconductor die.
One method includes the use of a bond on stitch ball (BSOB) wire bonding process. This technique is widely used for die to die bonding. It involves placing and bonding a gold ball bump at one end of a wire on a bond pad located on a silicon die. Another gold ball at the other end of the wire is bonded on a leadframe using ultrasonic energy, and then a wedge bonding process is performed on top of the gold bump.
There are some problems with the BSOB process. First, the BSOB process is slow and difficult to perform. Second, the high stress of the ball bumping process induces bond cratering. “Cratering” is a defect in which a portion of a die is torn loose by an excessive amount of ultrasonic wire-bonding energy. Third, it is difficult to consistently produce uniformly shaped gold balls.
Another method includes forming an impact cushioned copper stud bump on a silicon die. The impact cushioned copper stud bump prevents the silicon die from cracking during the copper stud bump forming process. This process uses a copper wire to form the copper stud bumps on the silicon die.
There are some problems associated with the impact cushioned copper stud bump process. First, like the above described gold ball process, this bumping process is slow and difficult to perform. Second, the copper stud that is formed is unprotected and is prone to oxidation. The presence of copper oxide in the copper stud bump increases the risk of excessive intermetallic compound formation when the copper stud is used with a lead-free solder.
Another method is described in Strandjord et al., “Low Cost Wafer Bumping Process for Flip Chip Applications (Electroless Nickel-Gold/Stencil Printing)”. In this article, a low cost method of solder bumping wafers is described. A solderable electroless nickel film is deposited over an aluminum pad. Nickel is plated to a desired height, and the nickel layer is coated with a thin immersion layer of gold.
There are some problems with this low cost wafer bumping process. First, in this process, nickel is used as a bump material. Higher resistance is expected, since nickel has a higher electrical resistance than copper. Nickel is also harder than copper, and therefore the embodiments described in Strandjord et al. are more prone to bond cratering during wirebonding.
Embodiments of the invention address these problems and other problems.
SUMMARY OF THE INVENTION
Embodiments of the invention are directed to bumped semiconductor dies and methods for making bumped semiconductor dies.
One embodiment of the invention is directed to a method comprising: (a) forming a plurality of copper bumps on a semiconductor die using a plating process, wherein the semiconductor die comprises a semiconductor device; (b) forming an adhesion layer on each copper bump in the plurality of copper bumps; and (c) forming a noble metal layer on each copper bump in the plurality of copper bumps, wherein the adhesion layer is between the noble metal layer and the copper bump.
Another embodiment of the invention is directed to a method comprising: (a) forming a plurality of copper bumps on a semiconductor die using a plating process, wherein the semiconductor die comprises a semiconductor device; (b) forming an adhesion layer comprising nickel on each copper bump in the plurality of copper bumps; (c) forming an oxidation resistant layer comprising gold on each copper bump in the plurality of copper bumps, wherein the adhesion layer is between the oxidation resistant layer and the copper bump to form a coated copper bump; and (d) bonding the coated copper bump to a conductive region of a circuit substrate using solder.
Another embodiment of the invention is directed to a semiconductor die package comprising: (a) a semiconductor die comprising a semiconductor device; (b) a plated copper bump on the semiconductor die, the plated copper bump having a top surface; (c) an adhesion layer on at least the top surface; and (d) an oxidation resistant layer on the adhesion layer.
These and other embodiments of the invention are described in further detail below.
REFERENCES:
patent: 4057659 (1977-11-01), Pammer et al.
patent: 5637916 (1997-06-01), Joshi
patent: 5765280 (1998-06-01), Joshi
patent: 5789809 (1998-08-01), Joshi
patent: 5895231 (1999-04-01), Choi et al.
patent: 5977783 (1999-11-01), Takayama et al.
patent: 6133634 (2000-10-01), Joshi
patent: 6294403 (2001-09-01), Joshi
patent: 6469384 (2002-10-01), Joshi
patent: 6489678 (2002-12-01), Joshi
patent: 6555923 (2003-04-01), Sasaki
patent: 6566749 (2003-05-01), Joshi et al.
patent: 6590287 (2003-07-01), Ohuchi
patent: 6600234 (2003-07-01), Kuwabara et al.
patent: 2002/0056906 (2002-05-01), Kajiwara et al.
patent: 2002/0063314 (2002-05-01), Huang et al.
patent: 2002/0151164 (2002-10-01), Jiang et al.
patent: 2002/0171157 (2002-11-01), Soga et al.
patent: 2003/0000067 (2003-01-01), Hori
patent: 2003/0030149 (2003-02-01), Miura et al.
patent: 2003/0042618 (2003-03-01), Nose et al.
Standjord, et al. Low Cost Wafer Bumping Processes for Flip Chip Applications (Electroless Nickel-Gold/Stencil Printing),IMAPS International Symposium on Microelectronics, Chicago, Illinois, pp. 18-33, (Oct. 24-27, 1999).
Cruz Erwin Victor R.
Joshi Rajeev
Tangpuz Consuelo
Clark Jasmine
Fairchild Semiconductor Corporation
Townsend and Townsend / and Crew LLP
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