Wafer level chip size packaged chip device with an N-shape...

Details Wafer level chip size packaged chip device with an N-shape... Wafer level chip size packaged chip device with an N-shape...

2008-07-01

2008-07-01

Lee, Eugene (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257SE23060, C257SE23061, C257SE23070, C257SE23145, C257SE21506, C257S692000, C438S597000

Reexamination Certificate

active

11559129

ABSTRACT:
The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional T-shape junction observed in Shellcase type wafer level chip size package technology, electrical connections between compatible pads and external leads are more reliable due to larger connection area than the counterpart in the T-shape junction.

REFERENCES:
patent: 6326689 (2001-12-01), Thomas
patent: 6429036 (2002-08-01), Nixon et al.
patent: 6646289 (2003-11-01), Badehi
patent: 6777767 (2004-08-01), Badehi
patent: 6972480 (2005-12-01), Zilber et al.
patent: 2002/0016024 (2002-02-01), Thomas

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