Wafer level chip size packaged chip device with a...

Details Wafer level chip size packaged chip device with a... Wafer level chip size packaged chip device with a...

2006-11-13

2010-02-16

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S690000, C257SE21499, C257SE23180

Reexamination Certificate

active

07663213

ABSTRACT:
The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.

REFERENCES:
patent: 6646289 (2003-11-01), Badehi
patent: 6777767 (2004-08-01), Badehi
patent: 6972480 (2005-12-01), Zilber et al.

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