Wafer level chip size package having rerouting layers

Details Wafer level chip size package having rerouting layers Wafer level chip size package having rerouting layers

2005-03-01

2005-03-01

Lee, Eddie (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S698000

Reexamination Certificate

active

06861742

ABSTRACT:
A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

REFERENCES:
patent: 6103552 (2000-08-01), Lin
patent: 6469393 (2002-10-01), Oya
patent: 6621164 (2003-09-01), Hwang et al.
patent: 20020076913 (2002-06-01), Lee
patent: 20020125568 (2002-09-01), Jiang et al.
patent: 20030153099 (2003-08-01), Jiang et al.
patent: 7-161761 (1995-06-01), None
patent: 11-40563 (1999-02-01), None
patent: WO 9923696 (1999-05-01), None
“Electronics Mount Technology Extra Edition 2000”, Gijyutsu-chyuosa-kai Corp., issued May 28, 2000, pp. 81-113.

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