Wafer-level chip scale package having stud bump and method...

Details Wafer-level chip scale package having stud bump and method... Wafer-level chip scale package having stud bump and method...

2002-11-15

2011-11-15

Clark, Sheila V (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S781000, C438S614000

Reexamination Certificate

active

08058735

ABSTRACT:
A wafer level chip scale package having stud bumps and a method for fabricating the same are described. The wafer level chip scale package includes a silicon substrate having a passivation layer and a chip pad on its top surface; a stud bump being formed on the chip pad and encircled by a first insulating layer; a re-distributed line (RDL) pattern being formed on the same horizontal surface as the first insulating layer and the stud bump, the RDL pattern for connecting the stud bump and a solder bump; a second insulating layer for insulating the RDL pattern so that a portion of the RDL pattern that is connected with the solder bump is exposed; and the solder bump being attached to the exposed portion if the RDL pattern.

REFERENCES:
patent: 5092033 (1992-03-01), Nishiguchi et al.
patent: 5501004 (1996-03-01), Onitsuka
patent: 5559054 (1996-09-01), Adamjee
patent: 5877549 (1999-03-01), Kim
patent: 5925931 (1999-07-01), Yamamoto
patent: 5928458 (1999-07-01), Aschenbrenner et al.
patent: 5949142 (1999-09-01), Otsuka
patent: 5986334 (1999-11-01), Lee
patent: 6013948 (2000-01-01), Akram et al.
patent: 6039896 (2000-03-01), Miyamoto et al.
patent: 6111317 (2000-08-01), Okada et al.
patent: 6150717 (2000-11-01), Wood et al.
patent: 6187615 (2001-02-01), Kim et al.
patent: 6190509 (2001-02-01), Haba
patent: 6239482 (2001-05-01), Fillion et al.
patent: 6252301 (2001-06-01), Gilleo et al.
patent: 6287893 (2001-09-01), Elenius et al.
patent: 6294405 (2001-09-01), Higgins, III
patent: 6300675 (2001-10-01), Tamai
patent: 6336990 (2002-01-01), Tanaka et al.
patent: 6350668 (2002-02-01), Chakravorty
patent: 6362087 (2002-03-01), Wang et al.
patent: 6368896 (2002-04-01), Farnworth et al.
patent: 6392305 (2002-05-01), Huang et al.
patent: 6396557 (2002-05-01), Tajima
patent: 6407459 (2002-06-01), Kwon et al.
patent: 6407508 (2002-06-01), Kawada et al.
patent: 6417089 (2002-07-01), Kim et al.
patent: 6441498 (2002-08-01), Song
patent: 6468830 (2002-10-01), Carson
patent: 6509634 (2003-01-01), Lee et al.
patent: 6512298 (2003-01-01), Sahara et al.
patent: 6518091 (2003-02-01), Haba
patent: 6518097 (2003-02-01), Yim et al.
patent: 6528344 (2003-03-01), Kang
patent: 6549413 (2003-04-01), Karnezos et al.
patent: 6555917 (2003-04-01), Heo
patent: 6566748 (2003-05-01), Shimizu et al.
patent: 6577008 (2003-06-01), Lam et al.
patent: 6590295 (2003-07-01), Liao et al.
patent: 6611052 (2003-08-01), Poo et al.
patent: 6621164 (2003-09-01), Hwang et al.
patent: 6621286 (2003-09-01), Takada et al.
patent: 2004/0191955 (2004-09-01), Joshi et al.
patent: 2005/0012225 (2005-01-01), Choi et al.
patent: 2005/0176233 (2005-08-01), Joshi et al.
patent: 2001-0009429 (2001-02-01), None
patent: 2001-0009564 (2001-02-01), None
John H. Lau(Ed.),Flip Chip Technologies(1996), pp. 301-314, McGraw-Hill, Boston, Massachusetts, USA.

Affiliated with

Also associated with

Rating

Wafer-level chip scale package having stud bump and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer-level chip scale package having stud bump and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer-level chip scale package having stud bump and method... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4282765