Wafer level chip scale package having a gap and method for...

Details Wafer level chip scale package having a gap and method for... Wafer level chip scale package having a gap and method for...

2007-04-17

2007-04-17

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S773000, C257S778000, C257SE23023, C438S613000

Reexamination Certificate

active

11186763

ABSTRACT:
A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

REFERENCES:
patent: 2002/0175409 (2002-11-01), Tsubosaki
patent: 2003/0052156 (2003-03-01), Kim et al.
patent: 2000-228423 (2000-08-01), None
patent: 1020020000692 (2002-01-01), None
patent: 1020030068376 (2003-08-01), None

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