Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2009-01-07
2009-12-15
Zarneke, David A (Department: 2891)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S111000, C257SE21514
Reexamination Certificate
active
07632719
ABSTRACT:
A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die.
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Choi Seung Yong
Joshi Rajeev
Kim Ji Hwan
Park Min Hyo
Fairchild Korea Semiconductor Ltd
Horton Kenneth E.
Kirton & McConkie
Zarneke David A
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