Wafer level chip scale package

Details Wafer level chip scale package Wafer level chip scale package

2011-01-04

2011-01-04

Chambliss, Alonzo (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With semiconductor element forming part

C257S701000, C257S774000, C257S786000, C257SE23011, C257SE23019, C257SE23145, C438S110000, C438S125000

Reexamination Certificate

active

07863719

ABSTRACT:
A semiconductor device of the invention includes a semiconductor substrate having a first insulating section formed on one surface thereof. A first conductive section is disposed on the one surface of the semiconductor substrate. A second insulating section is superimposed over the first insulating section and covers the first conductive section. A second conductive section is superimposed over the second insulating section. A third insulating section is disposed over the second insulating section and covers the second conductive section. These first conductive section, second insulating section, second conductive section, third insulating section, and terminal altogether constitute a structure. A third opening is formed between adjacent structures. The third opening is formed passing through the third and second insulating sections to expose the first insulating section.

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patent: 2005/0194687 (2005-09-01), Yamaguchi
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patent: 2004207368 (2004-07-01), None
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