Low power memory control circuits and methods

Details Low power memory control circuits and methods Low power memory control circuits and methods

2011-04-19

2011-04-19

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S205000, C365S207000, C365S208000, C365S189050, C365S189090, C365S226000

Reexamination Certificate

active

07929367

ABSTRACT:
Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.

REFERENCES:
patent: 5687123 (1997-11-01), Hidaka et al.
patent: 5696724 (1997-12-01), Koh et al.
patent: 5805508 (1998-09-01), Tobita
patent: 5814851 (1998-09-01), Suh
patent: 5889718 (1999-03-01), Kitamoto et al.
patent: 5991216 (1999-11-01), Raad et al.
patent: 6058061 (2000-05-01), Ooishi
patent: 6205068 (2001-03-01), Yoon
patent: 6307773 (2001-10-01), Smith
patent: 6314028 (2001-11-01), Kono
patent: 6337824 (2002-01-01), Kono et al.
patent: 6385115 (2002-05-01), Nakai
patent: 6424585 (2002-07-01), Ooishi
patent: 6452854 (2002-09-01), Kato et al.
patent: 6459639 (2002-10-01), Nishimura
patent: 6501696 (2002-12-01), Mnich et al.
patent: 6535443 (2003-03-01), Ou Yang et al.
patent: 6700826 (2004-03-01), Ito
patent: 6819600 (2004-11-01), Sim
patent: 6850454 (2005-02-01), Kuge et al.
patent: 6917551 (2005-07-01), Jeong
patent: 7002863 (2006-02-01), Joo
patent: 7002864 (2006-02-01), Kim et al.
patent: 7023721 (2006-04-01), Itoh et al.
patent: 7027334 (2006-04-01), Ikehashi et al.
patent: 7088629 (2006-08-01), Ohsawa
patent: 7209399 (2007-04-01), Chun et al.
patent: 7327627 (2008-02-01), Kawabata et al.
patent: 7330388 (2008-02-01), Chapman et al.
patent: 7345939 (2008-03-01), Lee et al.
patent: 7375999 (2008-05-01), Vogelsang
patent: 7408813 (2008-08-01), Lovett
patent: 7492654 (2009-02-01), Won et al.
patent: 1 164 595 (2001-12-01), None
patent: 2002 0045959 (2002-06-01), None
patent: 2003 0000844 (2003-01-01), None

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