Wafer level burn-in of SRAM

Details Wafer level burn-in of SRAM Wafer level burn-in of SRAM

2006-07-18

2006-07-18

Niebling, John F. (Department: 2812)

Static information storage and retrieval

Read/write circuit

Testing

C438S014000, C365S233100, C365S190000, C365S208000, C365S207000

Reexamination Certificate

active

07079433

ABSTRACT:
A wafer level burn-in method for static-random access memory. The SRAM memory has a plurality of word lines and a plurality of bit lines. The SRAM memory also has pull up circuits and equalizer circuits connected to various bit lines. All the word lines are switched on for testing any leakage in the gate dielectric layer. A high potential is applied to a bit line of every bit line pairs and a low potential is applied to the other bit line of the bit line pairs. The pull-up circuits and the equalizer circuits are shut down. The current at a steady state is used to judge the normality of an SRAM chip.

REFERENCES:
patent: 6038183 (2000-03-01), Tsukude
patent: 6198682 (2001-03-01), Proebsting
patent: 6205067 (2001-03-01), Tsukude
patent: 6208575 (2001-03-01), Proebsting
patent: 6212109 (2001-04-01), Proebsting
patent: 6240046 (2001-05-01), Proebsting

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